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1

Low frequency noise in advanced Si bulk and SOI MOSFETs

Jomaah J., Balestra F., Ghibaudo G.

Journal of Telecommunications and Information Technology

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2005

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nr 1

24-33

EN

A review of recent results concerning the low frequency noise in modern CMOS devices is given. The approaches such as the carrier number and the Hooge mobility fluctuations used for the analysis of the noise sources are presented and illustrated through experimental data obtained on advanced CMOS SOI and Si bulk generations. Furthermore, the impact on the electrical noise of the shrinking of CMOS devices in the deep submicron range is also shown. The main physical characteristics of random telegraph signals (RTS) observed in small area MOS transistors are reviewed. Experimental results obtained on 0.35-0.12 žm CMOS technologies are used to predict the trends for the noise in future CMOS technologies, e.g., 0.1 žm and beyond. For SOI MOSFETS, the main types of layout will be considered, that is floating body, DTMOS, and body-contact. Particular attention will be paid to the floating body effect that induces a kink-related excess noise, which superimposes a Lorentzian spectrum on the flicker noise.

2

Reliability of deep submicron MOSFETs

Balestra F.

Journal of Telecommunications and Information Technology

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2001

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nr 1

12-17

EN

In this work, a review of the reliability of n- and p-channel Si and SOI MOSFETs as a function of gate length and temperature is given. The main hot carrier effects and degradation are compared for bulk and SOI devices in a wide range of gate length, down to deep submicron. The worst case aging, defice lifetime and maximum drain bias that can be applied are addressed. The physical mechanisms and the emergence of new phenomena at the origin of the degradation are studied for advanced MOS transistors. The impact of the substrate bias is also outlined.

3

Performance and physical mechanisms in deep submicron SOI MOSFETs

Balestra F.

Electron Technology

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1999

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Vol. 32, No. 1/2

50-62

EN

The main electrical properties of advanced Silicon-On Insulator MOSFETs are addressed. The subthreshold and high field operations are analysed as a function of device architecture. The special SOI parastic phenomena, such as the floating body potential and temperature, are critically reviewed. The main limitation of submicron MOSFET are comparatively evaluated for various SOI strucures. Shot channel and hot carrier effects as well as the reliability of the SOI technology are investigated for gate lenght down to sub -0.1um.