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1
Content available Measurement and performance evaluation of a silicon on insulator pixel matrix
Ntavelis D., Harik L., Sallese J.-M., Kayal M., Hatzopoulos A.
International Journal of Microelectronics and Computer Science
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2010
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Vol. 1, nr 3
299-304
EN
A new technique for driving silicon-on-insulator pixel matrixes has been proposed in |1|, which was based on transient charge pumping for evacuating the extra photo-generated charges from the body of the transistor. An 8x8 pixel matrix was designed and fabricated using the above technique. In this paper, the measurement set-up is described and the performance evaluation procedure is given, together with results of its implementation on the fabricated pixel matrix. The results show the applicability of the charge pumping technique and the effective operation of the image sensor.
2
Content available The Impact of Externally Applied Mechanical Stress on Analog and RF Performances of SOI MOSFETs
Emam M., Houri S., Vanhoenacker-Janvier D., Raskin J.-P.
Journal of Telecommunications and Information Technology
|
2009
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nr 4
18-24
EN
This paper presents a complete study of the impact of mechanical stress on the performance of SOI MOSFETs. This investigation includes dc, analog and RF characteristics. Parameters of a small-signal equivalent circuit are also ex- tracted as a function of applied mechanical stress. Piezoresistance coefficientis shown to be a key element in describing the enhancement in the characteristics of the device due to mechanical stress.
3
Charakteryzacja struktur SOI za pomocą 3-poziomowej metody pompowania ładunku
Głuszko G., Łukasiak L., Jakubowski A.
Elektronika : konstrukcje, technologie, zastosowania
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2008
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Vol. 49, nr 1
72-74
PL
Przedstawiono próbę wyznaczenia energetycznego rozkładu gęstości pułapek powierzchniowych na górnej powierzchni granicznej dielektryk-półprzewodnik struktur SOI (diod PIN z bramką oraz tranzystorów MOS) za pomocą trójpoziomowej metody pompowania ładunku. Otrzymane wyniki zweryfikowano poprzez porównanie z rezultatami charakteryzacji dwupoziomową metodą pompowania ładunku.
EN
This paper presents for the first time the results of 3-level chargepumping measurements of SOI structures. Transistors with body contact as well as PIN gated diodes are used in measurements. The aim of these measurements is to provide information on the energy distribution of interface traps at the front Si-SiO2 interface.
4
Content available Characterization of SOI MOSFETs by means of charge-pumping
Głuszko G., Szostak S., Gottlob H., Lemme M., Łukasiak L.
Journal of Telecommunications and Information Technology
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2007
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nr 3
67-72
EN
This paper presents the results of charge-pumping measurements of SOI MOSFETs. The aim of these measurements is to provide information on the density of interface traps at the front and back Si-SiO2 interface. Three-level charge-pumping is used to obtain energy distribution of interface traps at front-interface.
5
Content available Standardization of the compact model coding: non-fully depleted SOI MOSFET example
Grabiński W., Tomaszewski D., Lemaitre L., Jakubowski A.
Journal of Telecommunications and Information Technology
|
2005
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nr 1
135-141
EN
The initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconductor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in particular going beyond the ITRS roadmap technological 100 nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC design process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented.
6
Content available An impact of physical phenomena on admittances of partially-depleted SOI MOSFETs
Tomaszewski D., Łukasiak L., Gibki J., Jakubowski A.
Journal of Telecommunications and Information Technology
|
2001
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nr 1
57-60
EN
An influence of the selected physical phenomena: impact ionization in silicon and time variation of internal electric field distribution in partially-depleted (PD) SOI MOSFETs on several C-V characteristics of these devices is presented. The role of avalanche multiplication in the so-called "pinch-off" region is discussed in a more detailed way. The analysis is done using a numerical solver of drift-diffusion equations in silicon devices and using an analytical model of the PD SOI MOSFETs. The calculations results exhibit the significance of proper modelling of the phenomena in the floating body area of these devices.
7
Content available A model of partially-depleted SOI MOSFETs in the subthreshold range
Tomaszewski D., Łukasiak L., Jakubowski A., Domański K.
Journal of Telecommunications and Information Technology
|
2001
|
nr 1
61-64
EN
A steady-state model of partially-depleted (PD) SOI MOSFETs I-V characteristics in subthreshold range is presented. Phenomena, which must be accounted for in current continuity equation, which is a key equation of the PD SOI MOSFETs model are summarized. A model of diffusion-based conduction in a weakly-inverted channel is described. This model takes into account channel length modulation, drift of carriers in the "pinch-off" region and avalanche multiplication triggered by these carriers. Characteristics of the presented model are shown and briefly discussed.
8
Content available Direct extraction techniques of microwave small-signal model and technological parameters for sub-quarter micron SOI MOSFETs
Goffioul M., Vanhoenacker D., Raskin J.P.
Journal of Telecommunications and Information Technology
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2000
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nr 3-4
59-66
EN
Original extraction techniques of microwave small-signal model and technological parameters for SOI MOSFETs are presented. The characterization method combines careful design of probing and calibration structures, rigorous in situ calibration and a powerful direct extraction method. The proposed characterization procedure is directly based on the physical meaning of each small-signal behavior of each model parameter versus bias conditions, the high frequency equivalent circuit can be simplified for extraction purposes. Biasing MOSFETs under depletion, strong inversion and saturation conditions, certain technological parameters and microwave small-signal elements can be extracted directly from the measured S-parameters. These new extraction techniques allow us to understand deeply the behavior of the sub-quarter micron SOI MOSFETs in microwave domain and to control their fabrication process.
9
Content available Comparison of microwave performances for sub-quarter micron fully- and partially-depleted SOI MOSFETs
Goffioul M., Dambrine G., Vanhoenacker D., Raskin J.P.
Journal of Telecommunications and Information Technology
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2000
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nr 3-4
72-80
EN
The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lenghts and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 žm FD SOI n-MOSFETs with a total gate width of 100 žm present a state-of-the-art minimum noise figure of 0.8 dB and high associated gain of 13 dB at 6 GHz for V(ds) = 0.75 V and P(dc) < 3 mW. A maximum extrapolated oscillation frequency of about 70 GHz has been obtained at V(ds) = 1 V and J(ds) = 100 mA/mm. This new generation of MOSFETs presents very good analogical and digital high speed performances with a low power consumption which make them extremely attractive for high frequency portable applications such as the wireless communications.
10
Content available An impact of frequency on capacitances of partially-depleted SOI MOSFETs
Tomaszewski D., Łukasik L., Zaręba A., Jakubowski A.
Journal of Telecommunications and Information Technology
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2000
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nr 3-4
67-71
EN
A non-quasi-static model of partially-depleted SOI MOSFETs is presented. Phenomena, which are particularly responsible for dependence of device admittances on frequency are briefly described. Several C-V characteristics of the SOI MOSFET calculated for a wide range of frequencies, preliminary results of numerical analysis and of measurements and brief analysis of the results are presented. Methods of model improvement are proposed.
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