Wyniki wyszukiwania - BazTech

1

Charakteryzacja tranzystorów typu FinFET na podstawie analizy statycznych charakterystyk prądowo-napięciowych

Gibki J., Łukasiak L., Jakubowski A.

Elektronika : konstrukcje, technologie, zastosowania

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2008

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Vol. 49, nr 9

24-26

PL

W artykule przedstawiono wyniki pomiarów i identyfikacji podstawowych parametrów statycznych tranzystorów typu FinFET. Szczególną uwagę zwrócono na wielkości prądu drenu w stanie słabej inwersji i prądu upływności bramki ważnych z punktu widzenia wytwarzania szybkich i energooszczędnych układów scalonych.

EN

The paper presents the results of measurements and extraction of basic FinFET parameters. Special attention is paid to drain-to-source leakage current and gate leakage current, important from the point of view of fast, low-power integrated circuits fabrication.

2

An impact of physical phenomena on admittances of partially-depleted SOI MOSFETs

Tomaszewski D., Łukasiak L., Gibki J., Jakubowski A.

Journal of Telecommunications and Information Technology

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2001

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nr 1

57-60

EN

An influence of the selected physical phenomena: impact ionization in silicon and time variation of internal electric field distribution in partially-depleted (PD) SOI MOSFETs on several C-V characteristics of these devices is presented. The role of avalanche multiplication in the so-called "pinch-off" region is discussed in a more detailed way. The analysis is done using a numerical solver of drift-diffusion equations in silicon devices and using an analytical model of the PD SOI MOSFETs. The calculations results exhibit the significance of proper modelling of the phenomena in the floating body area of these devices.

3

Characterization of SOI fabrication process using gated-diode measurements and TEM studies

Gibki J., Kątcki J., Ratajczak J., Łukasik L., Jakubowski A., Tomaszewski D.

Journal of Telecommunications and Information Technology

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2000

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nr 3-4

81-83

EN

SOI fabrication process was characterized using electrical and TEM methods. The investigated SOI structures included partially and fully depleted capacitors, gated diodes and transistors fabricated on SIMOX substrates. From C-V and I-V measurements of gated diodes, the following parameters of partially depleted structures were determined: doping concentration in both n- and p-type regions, average carrier generation lifetimes in the region under the gate and generation velocity at top and bottom surfaces of the active layer. Structures with short lifetime were studied using a transmission electron microscope. TEM studies indicate that the quality of the active layer in the investigated structures is good. Moreover, these studies were used to verify the thicknesses determined by means of electrical characterization methods.

4

Electrical characterization methods of SOI structures

Beck R. B., Ikraiam F., Gibki J., Łukasiak L., Zaręba A., Jakubowski A.

Electron Technology

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1999

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Vol. 32, No. 1/2

63-71

EN

This paper aims in addressing some of the issues related with the electrical characterization methods of SOI strucures. The electrical characterization methods are so far less developed than other techniques although they should offer better sensitivity and far more complex view of the properties of the SOI strucuters. The electrical characterization has proved its valuability in case of MOS structures. The complexity of the SOI structure is causing, however, certain prolems with analysis of the electrical characteristics. The purpose of this work is to comment on the pros and cons of particular characterization methods.

5

Determination of doping concentration and effective carrier lifetime in SOI structures from electrical measurements of gate controled diode

Gibki J., Jakubowski A., Łukasiak L., Tomaszewski D., Korwin-Pawłowski M.

Electron Technology

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1999

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Vol. 32, No. 1/2

116-118

EN

Methods of determination of the doping concentration and effective minority of differnt layers in a partially depleted SOI structures from I-V and C-V measurements of gate diodes have been described.

6

A small-signal non-quasi-static model of PD SOI MOSFETs

Tomaszewski D., Jakubowski A., Gibki J.

Electron Technology

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1999

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Vol. 32, No. 1/2

104-109

EN

This work presents a non-quasi-static small-signal of non-fully-depleted SOI MOSFET. It results from the explicit solution of a set of the Poisson and continuity in the appropriate areas of the device, Which has been obtained using so-called S³A approach. Our model is controlled by the same parameters, as the corresponding DC model. It accounts for the main phenomena in the device structure. It allows calculation of the full admittance matrix. The selected C-V characteristics of our model have been presented and compared with the data of the real device. The agreement is quite good. However a local misfit between the theoretical and experimental data requires further improvement of the model for the subthreshold and inversion bias conditions.

7

A model of I-V characteristcs of partially-depleted SOI MOSFETs

Tomaszewski D., Jakubowski A., Gibki J.

Electron Technology

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1999

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Vol. 32, No. 1/2

96-103

EN

This work presents a static model of a non-fully-depleted SOI MOSFET. It results from the explicit solutions of sets of the Poisson and continuity equations in the appropriate areas of the device, which have been obtained using S³ A approach. Our model accounts for the main phenomena in the device structure. The selected I-V characteristics of our model have been presented and compared with the data of the real device. The agreement is quite good. However a local misfit between the theoretical and experimental data requires further improvement of the model in the subthreshold and saturation bias conditions.

8

Wyznaczanie generacyjnego czasu życia nośników mniejszościowych struktur SOI z elektrycznych charakterystyk diody z bramką

Gibki J., Jakubowski A.

Elektronika : konstrukcje, technologie, zastosowania

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1998

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Vol. 39, nr 6

14-18

PL

Przedstawiono rezultaty badań diod z bramką zrealizowanych w technologii SOI. Analiza kształtu charakterystyk prądowo-napięciowych tych diod pozwala na wyznaczenie parametrów procesów generacyjno-rekombinacyjnych w strukturach, takich jak generacyjny czas życia oraz prędkości generacji powierzchniowej na dolnej i górnej granicy Si-SiO2. Opracowana metoda wydaje się być bardzo dokładnym i efektywnym narzędziem charakteryzacji technologii.

EN

In this paper a study of gate-controlled diodes fabricated in SOI technology has been presented. I-U and C-V measurements of gatecon-trolled diodes allowed the generation-recombination parameters to be determined, such as carrier lifetime and the generation velocity for both the front and back Si-SiO2 interfaces. The developed method seems to be an accurate and effective tool for technology characterisation.