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tom nr 132
26-33
EN
In this paper a two-phase recursive all-pass network for sampling-rate reduction is presented in which efficiency is achieved by simple binary scaling coefficients and by performing all necessary processing at the half sampling rate. This . network is formed as a sum of two parallel all-pass subf liters with phase shifts selected to add constructively in the passband and destructively in the stop band. The proposed structures offer very desirable properties in comparison to most published sigma-delta implementations which use a blend of simple comb filtering and decimated FIR filters for the post-modulator decimation filtering.
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tom nr 132
58-61
EN
Even an ideal delta-sigma modulator exhibits certain nonlinear behaviour. So its comprehensive analytical description has been both an absorbing and confusing task. Hence simulation and measurement are the key factor for a successful evaluation of the delta-sigma structure. This work is about high-quality decimation filters (digital sensors) for delta-sigma modulator investigations. They are based on a two-phase (two-branch) parallel structure using recursive allpasses which are particularly suitable for decimation by a factor of two. Moreover the repeated use of a basic decimation stage (BDS) makes this structure highly modular and well fittted for silicon implementation. An important BDS with only three coefficients (1/8, 9/16 and -1/16) has been presented in detail. Applied in the five stage decimaior and compatible with CMOS technology, it achieves a 20-bit processing accuracy for the passband of 20 kHz -without the design complexity and cost penalties incurred in alternative approaches. The paper includes some design results with performance evaluation under fixed point arithmetic. The in-situ developed software tools are also described.
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