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3 Prace Przemysłowego Instytutu Elektroniki

3 1998

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Oversampling sigma-delta converters modeling - a VHDL approach

100%

Baraniecki R. , Dąbrowski P. , Hejn K. , Rosiński A.

1998

tom nr 132

94-102

VHDL of me IEEE Std. 1076 has been designed for modeling of digital circuits, but there is a group of analog and mixed-signal circuits for which it can also be applied. For this group A/D oversampling sigma-delta converters belong - important components of many modem DSP circuits. In this paper some experiences considering VHDL modeling of sigma-delta converters are described. Some simulation results are enclosed to show efficiency of the presented approach. Its features are discussed in comparison to the design method of DSP circuits based on Signal Processing WorkSystem (SPW). This paper also contains examples of VHDL descriptions of this kind A/D converters.

Comparative evaluation of delta-sigma modulator structures used in the oversampling A/D converters

75%

Hejn K. , Kale I. , Kurek A.

1998

tom nr 132

35-40

The work reported in this paper focuses on computer simulations of Delta-Sigma modulators for oversampling Analog-to-Digltal (AD) converters. It calls into question the efficacy of traditional additive white noise techniques for modeling and analyzing the asymptotic statistical properties of quantization errors that arise in single and multistage oversampling modulators. The potential of the Comdisco - SPW on the SunSPARCl platform has been utilized for estimating gain error commonly used for data acquisition AD converters. It has been shown that the cascaded structure (type delta-sigma11 consisting of two first-order modulators) works much better than the common second-order modulator (type delta-sigma). The simulations results obtained have exhibited that the cascaded structure (type delta-sigma) with differential first-order modulators has the potential of 20 bit amplitude resolution within acoustic signal bandwidth.

A synthesizable decimation filter - VHDL macro

75%

Baraniecki R. , Dąbrowski P. , Hejn K. , Rosiński A.

1998

tom nr 132

104-111

The paper presents a design of a decimation filter - decimator, which can be used as a digital part of an oversampling sigma-delta analog-to-digital converter. The decimator model has been developed in VHDL as a macro parameterized with respect to the word length. A special architecture based on an arithmetic unit and a sequencer has been chosen to minimize the circuit area. Such an approach was possible due to the regular structure of the decimator.