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2 Prace Przemysłowego Instytutu Elektroniki

2 1998

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A decimation filter design from VHDL specification

100%

Baraniecki R. , Dąbrowski P. , Hejn K.

1998

tom nr 132

156-161

The paper presents a design of a decimation filter - decimator, which can be used as a digital part of an oversampling sigma-delta analog-to-digital converter. The decimator model has been developed in VHDL as a macro parameterized with respect to the word length. A special architecture based on an arithmetic unit aod a sequencer has been chosen to minimize the circuit area. Such an approach was possible due to the regular structure of the decimator.

Oversampling sigma-delta analog-to-digital converters modeling based on VHDL

80%

Baraniecki R. , Dąbrowski P. , Hejn K.

1998

tom nr 132

163-171

The paper presents a VHDL model of an oversampling sigma-delta analog-to-digital converter created on the behavioral hierarchy level. Although VHDL has been primarily devoted to digital circuit design, it can also be applied to certain mixed-signal circuits. The model of the analog part is as simple as possible and includes only necessary parameters that enable to determine the potential resolution of a converter. The model of the digital parttis described in the synthesizable subset of VHDL and parameterized according to the word length and the type of arithmetic applied. The validation process of the converter model is also shown. It is performed by a VHDL simulator and a postprocessor tool enabling to carry out FFT. Simulation results enclosed prove the efficiency of the design approach presented.