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1

Comparison of microwave performances for sub-quarter micron fully- and partially-depleted SOI MOSFETs

Goffioul M., Dambrine G., Vanhoenacker D., Raskin J.P.

Journal of Telecommunications and Information Technology

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2000

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nr 3-4

72-80

EN

The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lenghts and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 žm FD SOI n-MOSFETs with a total gate width of 100 žm present a state-of-the-art minimum noise figure of 0.8 dB and high associated gain of 13 dB at 6 GHz for V(ds) = 0.75 V and P(dc) < 3 mW. A maximum extrapolated oscillation frequency of about 70 GHz has been obtained at V(ds) = 1 V and J(ds) = 100 mA/mm. This new generation of MOSFETs presents very good analogical and digital high speed performances with a low power consumption which make them extremely attractive for high frequency portable applications such as the wireless communications.

2

High frequency four noise parameters of silicon-on-insulator-based technology MOSFET : prospects for application to low noise RF intergrated circuits

Dambrine G., Raskin J. P., Picheta L., Vanhoenacker D., Colinge J. P., Cappy A.

Electron Technology

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1999

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Vol. 32, No. 1/2

81-87

EN

An exhaustive experimental study of the high frequency noise properties of MOSFET in Silicon-on-Insulator (SOI) technology is presented. Various gate geometries are fabricated to study the influence of effective channel length and gate finger width on the four noise parameters. The high level of MOSFET sensitivity to the minimum noise matching conditions is demonstrated. From experimental results, optimization ways to realize ultra low noise amplifiers are discussed. The capability of the fully depleted standard SOI CMOS process for realizing low noise amplifiers for multigigahertz portable communication systems is shown. A minimum noise figure of about 0.7 dB and an available gain of 15 dB at 2 GHz have been obtained in the case of 0.6 µm effective gate length processes for applications in upper frequency range.

3

Accurate SOI MOSFET characterization at microwave frequencies

Raskin J. P., Dambrine G., Vanhoenacker D.

Electron Technology

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1999

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Vol. 32, No. 1/2

72-80

EN

The maturation of low cost SOI MOSFET technology in the microwave domain has brought about a need to develop specific characterization techniques. An original scheme is presented, which, by combining careful desigtn of probing and calibration structures, rigourous in situ calibration, and a new powerful direct extraction method, allows reliable identification of the parameters of the non-quasistatic small-signal model for MOSFET's. The extracted models is shown to be valid up to 40 GHz.