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2 2011

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Implementacja w układach FPGA wybranych fragmentów metody szybkiej segmentacji obrazów

Żurek D., Wielgosz M., Jamro E., Wiatr K.

Pomiary Automatyka Kontrola

2011

R. 57, nr 8

871-873

Prezentowane w pracy badania dotyczą segmentacji obrazów metodą wektorów wspierających (ang. Support Vector Machine - SVM). Metoda ta opiera się na grupie kilkunastu wektorów wspierających, które posiadają cechy wybranych obiektów w obrazie. Implementacja przedstawionej procedury klasyfikacji wektorów wspierających została wykona zarówno programowo w języku C++ na procesorze ogólnego przeznaczenia AMD AthlonII P320 Dual-Core2.10 GHz, jak i sprzętowo w języku VHDL. Moduł klasyfikacji wektorów wspierających został zaimplementowany w układzie Xilinx Spartan 6.

The paper presents preliminary implementation results of image segmentation for the SVM (Support Vector Machine) algorithm. SVM is a dedicated mathematical formula which allows extracting selective objects from an input picture and assign them to an appropriate class. Consequently, a black and white images reflecting occurrence of the desired feature are derived from an original picture fed into the classifier. This work is primarily focused on the FPGA implementation aspects of the algorithm as well as on comparison of the hardware and software performance. A human skin classifier was used as an example and implemented both in AMD AthlonII P320 Dual-Core2.10 GHz and Xilinx Spartan 6 FPGA. It is worth emphasizing that the critical hardware components were designed using HDL, whereas the less demanding standard ones such as communication interfaces, FIFO, FSMs were implemented in HLL (High Level Language). Such an approach allowed both shortening the design time and preserving high performance of the hardware classification module. This work is a part of the Synat project embracing several initiatives aiming at creation of a repository of images to which are to be assigned descriptive name according to their contents. Such a database of tagged images will significantly reduce the search time, since only picture tags will be processed instead of images, so the process will involve simple string operations rather than image recognition. The project is a huge challenge due to an immense volume of data collected over the past years denoted today as the Internet resources. Therefore, the core part of the undertaking is to design andimplement a classification system which should be both reliable and fast. In order to achieve the high performance of a search engine, the most computationally intensive operations are to be ported to hardware.

Methodology for Implementing Scalable Run-Time Reconfigurable Devices

Kotynia Ł., Amrozik P., Napieralski A.

International Journal of Electronics and Telecommunications

2011

Vol. 57, No. 2

177-183

The aim of this paper is to present the implementation methodology for an ASIC constituting the fine-grained array of dynamically reconfigurable processing elements. This methodology was developed during the work on a device which can operate as a typical Field Programmable Gate Array (FPGA) with some bio-inspired features or as a multi-core Single Instruction Multiple Data (SIMD) processor. Such high diversity of possible operating modes makes the design implementation extremely demanding. As a consequence, the comprehensive study and analysis of the different possible implementation techniques in this case allowed us to formulate a consistent and complete methodology that can be applied to other systems of similar structure.