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1

Programmable Analog Hard Real-Time Controller

Piłat A., Klocek J.

Przegląd Elektrotechniczny

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2013

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R. 89, nr 3a

38--46

EN

This elaboration describes the structure of the Programmable Analog Controller (PAC), its configuration, features and limitations. This universal hardware platform based on analog signal processors is dedicated to many scientific and industrial applications. This reconfigurable apparatus is suitable for computation, diagnosis and control tasks processed in the hardware layer in hard real-time regime. The main feature of the presented hardware-software solution is flexibility for applications determined by a configurable number of inputs and outputs as well as functionality. The modular construction allows to adapt the apparatus for the purpose of monitoring, control and signal processing tasks. Such a device can be easily configured to a dedicated application. The detailed description of available modules is given to show the computing and signal processing power.

PL

Niniejsze opracowanie przedstawia Programowalny Sterownik Analogowy (PAC), jego konfigurację, możliwości i ograniczenia. Opracowana uniwersalna platforma sprzętowa wykorzystująca procesory analogowe jest dedykowana do prac badawczych jak i zastosowań przemysłowych. Aparatura jest w pełni konfigurowana sprzętowo i programowo, a jej modułowa architektura pozwala na elastyczne zastosowanie urządzenia. Szczegółowy opis modułów pokazuje możliwości aparatury.

2

Synteza diagramu LD z operacjami arytmetycznymi przeznaczona dla układów FPGA

Milik A.

Pomiary Automatyka Kontrola

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2012

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R. 58, nr 7

617-619

PL

W artykule przedstawiono automatyczną metodę syntezy układu sterowania danego w postaci diagramu stykowego LD lub listy instrukcji IL do sprzętowego układu sterowania implementowanego w układzie FPGA. Zaproponowana metoda pozwala uzyskać sprzętowy układ sterowania zachowujący sekwencyjne własności przetwarzania wynikające z zapisu LD i IL. Przedstawiony algorytm syntezy pozwala na dokonanie syntezy operacji logicznych i arytmetycznych. Istotnymi celami opracowanego algorytmu jest masowe przetwarzanie, redukcja cykli obliczeniowych oraz odwzorowanie w ograniczonej liczbie zasobów operacji arytmetycznych.

EN

The paper presents the synthesis algorithm of a ladder diagram (LD) or instruction list (IL) into a reconfigurable logic controller implemented in FPGA [5, 8, 9]. The algorithm incorporates synthesis of Boolean and fixed point arithmetic operations. It utilizes the intermediate form of the data flow graph (DFG) [4, 6]. PLCs introduce variable dependencies caused by serial processing of LD (Fig. 1). It has been proved that appropriate distribution of feedback signals allows implementing LD logic dependencies during a single calculation cycle (Fig. 2). The LD diagram is compiled into DFG that records variable dependencies. The presented optimization allows reducing the controller complexity and its response time in comparison to solutions presented in [2, 3] (Fig. 3). Arithmetic operations introduce larger implementation complexity and require more time to calculate than logic operation. The DFG generated from LD or IL is used for scheduling and mapping (Fig. 4). The scheduling and mapping procedure assumes the limited number of arithmetic resources while logic operations are allocated without constraints. The scheduling procedure takes into account operation execution timing (Fig. 4C). The obtained circuit after scheduling with arithmetic operations may require more than one cycle to complete all operations in comparison to the model limited only to logic operations. The presented synthesis procedure enables obtainment of fully functional hardware implementation of the controller given by LD or IL with massively parallel processing and a very short response time (1 to several clock cycles).

3

Synthesis and Implementation of Reconfigurable PLC on FPGA Platform

Milik A., Hrynkiewicz E.

International Journal of Electronics and Telecommunications

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2012

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Vol, 58, No. 1

85-94

EN

The paper presents a set of algorithms dedicated for synthesis of reconfigurable logic controllers implemented on FPGA platform and programmed according to IEC1131 and EN61131. The program is compiled to hardware structure with a massive parallel processing. The developed method automatically allocates resources and operations. It controls resource usage and operation timing. Using mixed concept of operation allocation that considers operation timing and forms combinatorial chains of operations number of execution cycles can be reduced. An example of logic functions, PID controller and mixed arithmetic and logic programming examples are considered. Introducing the automatic implementation method allows flexible implementing the control algorithms. The maximal possible parallelism (limited only by the algorithm dependencies and available resources) is introduced.

4

Implementacja wyrażeń arytmetycznych w rekonfigurowalnych sterownikach logicznych

Milik A., Pułka A.

Pomiary Automatyka Kontrola

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2011

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R. 57, nr 8

842-844

PL

W artykule przedstawiono metodę odwzorowania operacji arytmetycznych przeznaczoną dla rekonfigurowalnych sterowników logicznych. Istotą opracowanej metody jest wykorzystanie własności układów sprzętowych oraz architektury FPGA. W procesie implementacji brane są pod uwagę czas realizacji obliczeń oraz ograniczone zasoby logiczne. W oparciu o metodę szacowania czasu propagacji zrealizowano metodę łańcuchowego łączenia operacji kombinacyjnych pozwalającą na wykonanie wielu operacji w cyklu obliczeniowym.

EN

The paper presents a package for arithmetic operation synthesis dedicated for reconfigurable logic controllers. Different representations (graphical or textual) commonly used are handled. The synthesis process starts from transforming algorithm representation into a data flow graph. The constant reduction and the tree height reduction optimization method are applied to the flow graph (Fig. 2). The developed method combines the ALAP and list allocation strategies with original elements. The main constraint is put to the number of available logic resources that can be allocated. The procedure attempts to allocate resources assuring it proper utilization in a calculation process. Together with resource allocation the operation scheduling is performed. During operation assignment the propagation time based concept of operation scheduling is used. The proposed method allows using sequential and combinatorial units. Operations are chained inside one state until total combinatorial propagation time does not exceed the assumed cycle time. This allows reducing the required number of calculation cycles by introducing combinatorial chains of operations (Figs. 3 and 4). Finally, an example of PID controller implementation is considered and compared with previous manual implementations (Fig. 5). Introducing the automatic implementation method allows reducing radically the calculation time (2.18 times) with little increase in hardware resources (+18%) (see Tab. 1).

5

Large Data Stream Processing : Embedded Systems Design Challenges

Handzlik A., Jabłonski A.

International Journal of Electronics and Telecommunications

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2010

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Vol. 56, No. 2

107-110

EN

The following paper describes an application of reconfigurable hardware architectures for processing of huge data streams. Radar, sonar and high speed internet networks are typical sources of data that require extreme computing power and resources to enable real time acquisition, processing and management. An approach to monitoring of real time multi-gigabit internet network has been described as a practical application of FPGA based board, designed for fast data processing.

6

Adaptive and Evolvable Hardware and Systems: The State of the Art and the Prospectus for Future Development

Negoita M. G., Sekanina L., Stoica A.

Journal of Automation Mobile Robotics and Intelligent Systems

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2009

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Vol. 3, No. 2

70-75

EN

This paper is an overview on the Evolvable Hardware (EHW) - the exciting and rapidly expanding industrial application area of the Evolutionary Computing (EC), of the Genetic Algorithms especially. The content of the work has the following structure: the first part includes generalities on industrial applications of EC, and the importance of EHW in this frame; the second part presents the outstanding technological support making possible the implementation of system adaptation in hardware. Different kind of programmable circuits arrays are introduced. The third part tackles the most known EC based methods for EHW implementation; the fourth part deals with some concrete elements of the EHW design, including the current limits in evolutionary design of digital circuits. The last part is focused on some concluding remarks with regard to future perspectives of the area. A list of references used in this work was inserted at the end.