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1
Content available Efficiency of Spartan-7 FPGA devices in implementation of contemporary cryptographic algorithms
Sugier J.
Journal of Polish Safety and Reliability Association
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2018
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Vol. 9, No. 3
75--84
EN
Hardware implementations of cryptographic algorithms are ubiquitous in contemporary computer systems where they are used to ensure appropriate level of security e.g. in high-speed data transmission, authentication and access control, distributed cloud storage, etc.. In this paper we evaluate size and speed efficiency of FPGA implementations of selected popular cryptographic algorithms in the newest cost-sensitive Spartan-7 devices form Xilinx, Inc.. The investigated set of algorithms included four examples: the AES-128 standard symmetric block cipher, the BLAKE-256 hash function and two size variants of the KECCAK-f[b] compression function, b = 400 and 1600, with the larger variant being used as the core of the new SHA-3 standard. The main aim of this research was to provide a uniform and comparable implementation approach for all the ciphers so that the new potentials of the Spartan-7 internal architecture would be put to the test in realization of their specific cryptographic transformations and data distribution. Each of the four algorithms was implemented in five architectures: the basic iterative one (with one instance of the cipher round instantiated in hardware) plus two loop unrolled ones (with two and four or five rounds in hardware) and their two pipelined variants (with registers at the outputs of each round enabling parallel processing of multiple streams of data). Uniform implementation methodology applied to 20 cases of cipher & architecture combinations created a consistent testbed, producing comparable results which allowed to evaluate efficiency of the new hardware platform in implementation of the different algorithms in various unrolled and pipelined organizations.
2
Content available Implementing SHA-3 candidate BLAKE algorithm in Field Programmable Gate Arrays
Sugier J.
Journal of Polish Safety and Reliability Association
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2016
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Vol. 7, No. 1
193--200
EN
BLAKE is a cryptographic hash function proposed as a candidate in SHA-3 contest where he successfully qualified to the final round with other 4 candidates. Although it eventually lost to KECCAK it is still considered as a suitable solution with good cryptographic strength and great performance especially in software realizations. For these advantages BLAKE is commonly selected to be a hash function of choice in many contemporary IT systems in applications like digital signatures or message authentication. The purpose of this paper is to evaluate how the algorithm is suitable to be implemented in hardware using low-cost Field Programmable Gate Array (FPGA) devices, particularly to test how efficiently its complex internal transformations can be realized with FPGA resources when overall size of the implementation grows substantially with multiple rounds of the cipher running in parallel in hardware and capacity of the configurable array is used up to its limits. The study was made using the set of 7 different architectures with different loop unrolling factors and with optional application of pipelining, with each architecture being implemented in two popular families of FPGA devices from Xilinx. Investigation of the internal characteristic of the implementations generated by the tools helped in analysis how the fundamental mechanism of loop unrolling with or without pipelining works in case of this particular cipher.
3
Content available Efficiency of FPGA architectures in implementations of AES, Salsa20 and Keccak cryptographic algorithms
Sugier J.
Journal of Polish Safety and Reliability Association
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2015
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Vol. 6, No. 2
117--124
EN
The aim of this paper is to test efficiency of automatic implementation of selected cryptographic algorithms in two families of popular-grade FPGA devices from Xilinx: Spartan-3 and Spartan-6. The set of algorithms include the Advanced Encryption Standard (AES) used worldwide as a symmetric cipher along with two hash algorithms: Salsa20 (developed with ECRYPT Stream Cipher Project) and Keccak permutation function (core of the new SHA-3 standard). The ciphers were expressed in 5 architectures: the basic iterative one (one instance of a round in hardware) and its four derivatives created by loop unrolling and pipelining. With each of the architectures implemented in both Spartan devices this gave the total of 30 test cases, which, upon automatic implementation, created a comprehensive and consistent base for comparison of the ciphers, applied architectures and FPGA devices used for implementation.
4
Content available Pipelined scaling of signed residue numbers with the mixed-radix conversion in the programmable gate array
Czyżak M., Smyk R., Ulman Z.
Poznan University of Technology Academic Journals. Electrical Engineering
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2013
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No. 76
89--99
EN
In this work a scaling technique of signed residue numbers is proposed. The method is based on conversion to the Mixed-Radix System(MRS) adapted for the FPGA implementation. The scaling factor is assumed to be a moduli product from the Residue Number System (RNS) base. Scaling is performed by scaling of terms of the mixed-radix expansion, generation of residue representations of scaled terms, binary addition of these representations and generation of residues for all moduli. The sign is detected on the basis of the value of the most significant coefficient of the MRS representation. For negative numbers their residues are adequately corrected. The basic blocks of the scaler are realized in the form of the modified two-operand modulo adders with included additional multiply and modulo reduction operations. The pipelined realization of the scaler in the Xilinx environment is shown and analyzed with respect to hardware amount and maximum pipelining frequency. The design is based on the LUTs(26x 1) that simulate small RAMs serving as the main component for the look-up realization.
5
Content available Pipelined division of signed numbers with the use of residue arithmetic for small number range with the programmable gate array
Smyk R., Ulman Z., Czyżak M.
Poznan University of Technology Academic Journals. Electrical Engineering
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2013
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No. 76
117--126
EN
In this work an architecture of the pipelined signed residue divider for the small number range is presented. Its operation is based on reciprocal calculation and multiplication by the dividend. The divisor in the signed binary form is used to compute the approximated reciprocal in the residue form by the table look-up. In order to limit the look-up table address an algoritm based on segmentation of the divisor into two segments is used. The approximate reciprocal transformed to residue representation with the proper sign is stored in look-up tables. During operation it is multiplied by the dividend in the residue form and subsequently scaled. The pipelined realization of the divider in the FPGA environment is also shown.
6
Content available Low-cost hardware implementations of Salsa20 stream cipher in programmable devices
Sugier J.
Journal of Polish Safety and Reliability Association
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2013
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Vol. 4, No. 1
121--128
EN
Salsa20 is a 256-bit stream cipher that has been proposed to eSTREAM, ECRYPT Stream Cipher Project, and is considered to be one of the most secure and relatively fastest proposals. This paper describes hardware implementation of various architectures of this cipher in popular Field Programmable Gate Arrays (FPGA). The implemented architectures are based on the loop-unrolled data flow organization and after pipelining they can reach the throughput in the range of 20 – 30 Gbps even after fully automatic implementation in popular low-cost families of Spartan-3 and Spartan-6 from Xilinx. More resource-limited iterative architectures achieve speed of 1 – 2 Gbps. The results that are included in this work present potential of the algorithm when it is implemented in a specific FPGA environment and provide some information for evaluation of cipher effectiveness in contemporary popular programmable devices.
7
Content available Measurement aspects of genome pattern investigations - hardware implementation
Pułka A., Milik A.
Metrology and Measurement Systems
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2012
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Vol. 19, nr 1
49-62
EN
The work presented in the paper concerns a very important problem of searching for string alignments. The authors show that the problem of a genome pattern alignment could be interpreted and defined as a measuring task, where the distance between two (or more) patterns is investigated. The problem originates from modern computation biology. Hardware-based implementations have been driving out software solutions in the field recently. The complex programmable devices have become very commonly applied. The paper introduces a new, optimized approach based on the Smith-Waterman dynamic programming algorithm. The original algorithm is modified in order to simplify data-path processing and take advantage of the properties offered by FPGA devices. The results obtained with the proposed methodology allow to reduce the size of the functional block and radically speed up the processing time. This approach is very competitive compared with other related works.
8
Content available Implementation of symmetric block ciphers in popular-grade FPGA devices
Sugier J.
Journal of Polish Safety and Reliability Association
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2012
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Vol. 3, No. 2
179--188
EN
In this paper we discuss hardware implementations of the two best ciphers in the AES contest – the winner Rijndael and the Serpent – in low-cost, popular Field-Programmable Gate Arrays (FPGA). After presenting the elementary operations of the ciphers and organization of their processing flows we concentrate on specific issues of their implementations in two selected families of popular-grade FPGA devices from Xilinx: currently the most common Spartan-6 and its direct predecessor Spartan-3. The discussion concentrates on differences in resources offered by these two families and on efficient implementation of the elementary transformations of the two ciphers. For case studies we propose a selection of different architectures (combinational, pipelined and iterative) for the encoding units and, after their implementation, we compare size requirements and performance parameters of the two ciphers across different architectures and on different FPGA platforms.
9
Content available An Efficient Hardware Implementation of Smith-Waterman Algorithm Based on the Incremental Approach
Pułka A., Milik A.
International Journal of Electronics and Telecommunications
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2011
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Vol. 57, No. 4
489-496
EN
The paper presents optimized hardware structure applied to genome alignment search. The proposed methodology is based on dynamic programming. The authors show how starting from the original Smith-Waterman approach, the algorithm can be optimized and the evaluation process simplified and speeded-up. The main idea is based on the observations of growth trends in the adjacent cells of the systolic array, which leads to the incremental approach. Moreover various coding styles are discussed and the best technique allowing further reduction of resources is selected. The entire processing unit utilizes fully pipelined structure that is well balanced trade-off between performance and resource requirements. The proposed technique is implemented in modern FPGA structures and obtained results proved efficiency of the methodology comparing to other approaches in the field.
10
Content available Weryfikacja reguł bezpieczeństwa wspomagana mechanizmami pamięci podręcznej w sprzętowej implementacji systemu bezpieczeństwa typu firewall
Sułkowski G., Twardy M., Wiatr K.
Pomiary Automatyka Kontrola
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2008
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R. 54, nr 8
511-513
PL
W niniejszym artykule autorzy dokonują przeglądu istniejących algorytmów klasyfikacji pakietów celem adaptacji najodpowiedniejszego spośród nich dla potrzeb budowanego systemu zabezpieczeń sieciowych klasy Firewall. Równocześnie prezentują koncepcje zwiększenia całkowitej wydajności proponowanego rozwiązania poprzez zastosowanie dodatkowych mechanizmów wykorzystujących m.in. pamięci podręczne, potokowość oraz zrównoleglenie przetwarzania danych.
EN
In this paper authors present their research into the actual state of the hardware implemented packet classification algorithms for the adaptation into their implementation of the hardware Firewall security system. The paper also describes the idea of enhancing the overall processing efficiency by using additional mechanisms like local cache memory, pipelining and parallel processing.
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