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1
Content available remote Liczby zespolone - postać algebraiczna w wersji lekkostrawnej
Maciaszczyk Martyna
MINUT Matematyka i Informatyka na Uczelniach Technicznych
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2022
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Nr 4
70-80
PL
Praktycznie na każdym kierunku studiów na uczelniach technicznych pojawiają się liczby zespolone-tajemnicze wyrażenie z jednostką urojoną. W tym artykule postaram się uchylić rąbka tajemnicy, jak rozwiązywać niektóre zadania z liczbami zespolonymi przedstawionymi w postaci algebraicznej.
2
Content available remote Combinatorial Etude
Stoenchev Miroslav, Todorov Venelin
Annals of Computer Science and Information Systems
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2021
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Vol. 25
231--234
EN
The purpose of this article is to consider a special class of combinatorial problems, the so called Prouhet-Tarry Escot problem, solution of which is realized by constructing finite sequences of ±1. For example, for fixed p∈N, is well known the existence of np∈N with the property: any set of np consecutive integers can be divided into 2 sets, with equal sums of its p[th] powers. The considered property remains valid also for sets of finite arithmetic progressions of complex numbers.
3
Content available remote A Function Elimination Method for Checking Satisfiability of Arithmetical Logics
Castiglioni V., Lanotte R., Tini S.
Fundamenta Informaticae
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2016
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Vol. 143, nr 1/2
51--71
EN
We study function elimination for Arithmetical Logics. We propose a method allowing substitution of functions occurring in a given formula with functions with less arity. We prove the correctness of the method and we use it to show the decidability of the satisfiability problem for two classes of formulas allowing linear and polynomial terms.
4
Content available Synteza diagramu LD z operacjami arytmetycznymi przeznaczona dla układów FPGA
Milik A.
Pomiary Automatyka Kontrola
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2012
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R. 58, nr 7
617-619
PL
W artykule przedstawiono automatyczną metodę syntezy układu sterowania danego w postaci diagramu stykowego LD lub listy instrukcji IL do sprzętowego układu sterowania implementowanego w układzie FPGA. Zaproponowana metoda pozwala uzyskać sprzętowy układ sterowania zachowujący sekwencyjne własności przetwarzania wynikające z zapisu LD i IL. Przedstawiony algorytm syntezy pozwala na dokonanie syntezy operacji logicznych i arytmetycznych. Istotnymi celami opracowanego algorytmu jest masowe przetwarzanie, redukcja cykli obliczeniowych oraz odwzorowanie w ograniczonej liczbie zasobów operacji arytmetycznych.
EN
The paper presents the synthesis algorithm of a ladder diagram (LD) or instruction list (IL) into a reconfigurable logic controller implemented in FPGA [5, 8, 9]. The algorithm incorporates synthesis of Boolean and fixed point arithmetic operations. It utilizes the intermediate form of the data flow graph (DFG) [4, 6]. PLCs introduce variable dependencies caused by serial processing of LD (Fig. 1). It has been proved that appropriate distribution of feedback signals allows implementing LD logic dependencies during a single calculation cycle (Fig. 2). The LD diagram is compiled into DFG that records variable dependencies. The presented optimization allows reducing the controller complexity and its response time in comparison to solutions presented in [2, 3] (Fig. 3). Arithmetic operations introduce larger implementation complexity and require more time to calculate than logic operation. The DFG generated from LD or IL is used for scheduling and mapping (Fig. 4). The scheduling and mapping procedure assumes the limited number of arithmetic resources while logic operations are allocated without constraints. The scheduling procedure takes into account operation execution timing (Fig. 4C). The obtained circuit after scheduling with arithmetic operations may require more than one cycle to complete all operations in comparison to the model limited only to logic operations. The presented synthesis procedure enables obtainment of fully functional hardware implementation of the controller given by LD or IL with massively parallel processing and a very short response time (1 to several clock cycles).
5
Content available Implementacja wyrażeń arytmetycznych w rekonfigurowalnych sterownikach logicznych
Milik A., Pułka A.
Pomiary Automatyka Kontrola
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2011
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R. 57, nr 8
842-844
PL
W artykule przedstawiono metodę odwzorowania operacji arytmetycznych przeznaczoną dla rekonfigurowalnych sterowników logicznych. Istotą opracowanej metody jest wykorzystanie własności układów sprzętowych oraz architektury FPGA. W procesie implementacji brane są pod uwagę czas realizacji obliczeń oraz ograniczone zasoby logiczne. W oparciu o metodę szacowania czasu propagacji zrealizowano metodę łańcuchowego łączenia operacji kombinacyjnych pozwalającą na wykonanie wielu operacji w cyklu obliczeniowym.
EN
The paper presents a package for arithmetic operation synthesis dedicated for reconfigurable logic controllers. Different representations (graphical or textual) commonly used are handled. The synthesis process starts from transforming algorithm representation into a data flow graph. The constant reduction and the tree height reduction optimization method are applied to the flow graph (Fig. 2). The developed method combines the ALAP and list allocation strategies with original elements. The main constraint is put to the number of available logic resources that can be allocated. The procedure attempts to allocate resources assuring it proper utilization in a calculation process. Together with resource allocation the operation scheduling is performed. During operation assignment the propagation time based concept of operation scheduling is used. The proposed method allows using sequential and combinatorial units. Operations are chained inside one state until total combinatorial propagation time does not exceed the assumed cycle time. This allows reducing the required number of calculation cycles by introducing combinatorial chains of operations (Figs. 3 and 4). Finally, an example of PID controller implementation is considered and compared with previous manual implementations (Fig. 5). Introducing the automatic implementation method allows reducing radically the calculation time (2.18 times) with little increase in hardware resources (+18%) (see Tab. 1).
6
Upraszczanie afinicznych relacji i zbiorów w celu podniesienia wydajności generowanego kodu równoległego
Pałkowski M.
Metody Informatyki Stosowanej
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2008
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nr 3 (Tom 16)
213--222
EN
A representation of relations and sets determines the amount of instructions and the form of loops in generated parallel code with using the Omega Calculator [1,2]. An unsimplified set of iterations may cause unnecessary instructions in parallel code and longer time of code execution. Algorithms of the simplification of relations and sets by means of the operation are presented. Under experiments, code of generated loops along with execution time is examined. The algorithms can be used also to reduce amount of one-conjunct relations and sets.
7
Content available remote Some aspects of teaching the concepts: arithmetic and weighted means at various levels of mathematical education
Bugajska-Jaszczołt B., Czajkowska M.
Scientific Issues of Jan Długosz University in Częstochowa. Mathematics
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2007
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Vol. 12
163-170
EN
We refer to selected problems of formulating the definitions of arithmetic and weighted means in secondary school and at a higher level. The first problem discussed here are the results of theoretical research. We compare the manner of formulating the definitions, in particular, the level of formalization of mathematical language. We present the differences between various definitions, found in the analyzed textbooks, in such aspects as: generality, degree and kind of complication of logical structure, and intuitions provoked by them. We underline qualitatively different objects defined by them - arithmetic mean of numbers and arithmetic mean of scalable feature, emphasizing the consequences.
8
Content available remote Finite Arithmetics
Krynicki M., Mostowski M., Zdanowski K.
Fundamenta Informaticae
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2007
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Vol. 81, nr 1-3
183-202
EN
The paper presents the current state of knowledge in the field of logical investigations of finite arithmetics. This is an attempt to summarize the ideas and results in this area. Some new results are presented - these are mainly generalizations of the earlier results related to properties of sl-theories and some nontrivial cases of FM-representability theorem.
9
Content available remote Sekwencja Farey’a, czyli jak geolog znalazł miejsce w historii matematyki
Biernacki W.
Wiadomości Naftowe i Gazownicze
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2006
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R. 9, Nr 9 (101)
14-18
10
Content available remote Influence of uncertainties and wrapping effect reduction in linear dynamical systems by affine arithmetic
Stręk T.
Vibrations in Physical Systems
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2004
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Vol. 21
361--364
11
Content available remote Some classes of linear quasigroups
Nĕmec P.
Scientific Issues of Jan Długosz University in Częstochowa. Mathematics
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1998
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Vol. 4
22-33
EN
Several important classes of quasigroups can be characterized by means of certain linear constructions (see e.g. [3], [4], [7], [8]). The first to investigate such linear quasigroups seems to be Toyoda [8] as early as in 1941, who showed that a quasigroup Q is medial iff there is an Abelian group Q(+), two automorphisms f,g of Q and an element a ∈ Q such that fg=gf and xy=f(x)+g(y)=+a for all x,y ∈ Q. Further, Belousov [1] (and independently Soublin [7] showed that a quasigroup Q is distributive iff there is a commutative Moufang loop Q(+) and an automorphism f of Q(+) such that 1 - f is an automorphism, f (x) + x € C(Q(+))} and xy=f(x) + (1-f)(y) for all x,y ∈ Q. As a further generalization in this direction, Kepka [3] proved that a quasigroup is trimedial (i.e., each sub quasigroup generated by at most three elements is medial) iff there is a commutative Moufang loop Q(+), two automorphisms f, g of Q(+) and an element a € C(Q(+)) such that fg = gf and xy = f (x) + g(y) + a for all x,y ∈ Q. These results naturally suggest an idea of defining an arithmetical form of a quasigroup Q as a quadruple (Q(+),,f, g,a) such that Q(+) is a commutative Moufang loop, f, g are automorphisms of Q(+), a E Q and xy = (f (x) + g(y)) + a for all x,y ∈ Q. We shall say that Q is a linear quasigroup if it has at least one arithmetical form. All possible arithmetical forms of a linear quasigroup were characterized in [5] and the structure of commutative Moufang loops occurring in different arithmetical forms of a linear quasigroup was investigated in [6]. This contribution is devoted to the description of some particular classes of linear quasigroups.
12
Content available remote Quasiarithmetic mean
Rys P., Zdráhal T.
Scientific Issues of Jan Długosz University in Częstochowa. Mathematics
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1998
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Vol. 4
8-15
EN
This talk through the mediation of easy motive examples gives reasons for proper establishing of the quasiarithmetic mean and gives instruction to solve practical problems that common aim is to find ,,an average" of certain values.
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