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1

Reducing the number of LUTs for Mealy FSMs with state transformation

Barkalov Alexander, Titarenko Larysa, Mielcarek Kamil

International Journal of Applied Mathematics and Computer Science

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2024

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Vol. 34, no. 1

167--178

EN

In many digital systems, various sequential blocks are used. This paper is devoted to the case where the model of a Mealy finite state machine (FSM) represents the behaviour of a sequential block. The chip area occupied by an FSM circuit is one of the most important characteristics used in logic synthesis. In this paper, a method is proposed which aims at reducing LUT counts for FPGA-based Mealy FSMs with transformation of state codes into FSM outputs. This is done using the combined state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed method leads to LUT-based Mealy FSM circuits having exactly three levels of logic blocks. Under certain conditions, each function for any logic level is represented by a circuit including a single LUT. The proposed approach is illustrated with an example of synthesis. The results of experiments conducted using standard benchmarks show that the proposed method produces LUT-based FSM circuits with significantly smaller LUT counts than is the case for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of binary codes into extended state codes). The LUT count is decreased by an average of 17.96 to 91.8%. Moreover, if some conditions are met, the decrease in the LUT count is accompanied with a slight improvement in the operating frequency compared with circuits based on extended state codes. The advantages of the proposed method multiply with increasing the numbers of FSM inputs and states.

2

The use of the GIS system in optimizing the costs of inspecting technical devices

Miłek Marzenna, Stanik Jerzy, Kiedrowicz Maciej, Napiórkowski Jarosław

GIS Odyssey Journal

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2023

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Vol. 3, no. 2

51--63

EN

Enterprises using cranes, HDS platforms, other handling equipment, or pressure equipment in their activities are subject to registration with the Office of Technical Inspection (UDT), which is obliged to conduct inspection activities on them. Inspections of technical devices are aimed at checking their technical condition. Approximately 1.3 million technical devices are currently subject to UDT supervision in Poland. Annually, UDT inspectors carry out over 1 million tests of technical devices, and the activities carried out by UDT translate into a constant reduction in the accident rate. All this takes place in conditions that require continuous work planning and scheduling. This article aims to present and discuss the use of open-source solutions for planning the work of teams carrying out inspection activities, along with the concept of their use.

3

An Efficient Two-phase Clocked Sequential Multiply : Accumulator Unit for Image Blurring

Samanth Rashmi, Nayak Subramanya G.

International Journal of Electronics and Telecommunications

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2022

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Vol. 68, No. 2

307--313

EN

The multiply-accumulator (MAC) unit is the basic integral computational block in every digital image and digital signal processor. As the demand grows, it is essential to design these units in an efficient manner to build a successful processor. By considering this into account, a power-efficient, high-speed MAC unit is presented in this paper. The proposed MAC unit is a combination of a two-phase clocked modified sequential multiplier and a carry-save adder (CSA) followed by an accumulator register. A novel two-phase clocked modified sequential multiplier is introduced in the multiplication stage to reduce the power and computation time. For image blurring, these multiplier and adder blocks are subsequently incorporated into the MAC unit. The experimental results demonstrated that the proposed design reduced the power consumption by 𝟓𝟐% and improved the computation time by 𝟒% than the conventional architectures. The developed MAC unit is implemented using 𝟏𝟖𝟎𝒏𝒎 standard CMOS technology using CADENCE RTL compiler, synthesized using XILINX ISE and the image blurring effect is analyzed using MATLAB.

4

Improving the LUT count for Mealy FSMs with transformation of output collections

Barkalov Alexander, Titarenko Larysa, Mazurkiewicz Małgorzata

International Journal of Applied Mathematics and Computer Science

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2022

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Vol. 32, no. 3

479--494

EN

A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state machines (FSMs) with transformation of collections of outputs into state codes. The reduction is achieved due to the use of two-component state codes. Such an approach allows reducing the number of state variables compared with FSMs based on extended codes. There are exactly three levels of LUTs in the resulting FSM circuit. Each partial function is represented by a single-LUT circuit. The proposed method is illustrated with an example of synthesis. The experiments were conducted using standard benchmarks. They show that the proposed method produces FSM circuits with significantly smaller LUT counts compared with those produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of output collection codes into extended state codes). The LUT count is decreased by, on average, from 9.86% to 59.64%. The improvement of the LUT count is accompanied by a slightly improved performance. The maximum operating frequency is increased, on average, from 2.74% to 12.93%. The advantages of the proposed method become more pronounced with increasing values of FSM inputs and state variables.

5

Improving characteristics of LUT-based Mealy FSMs

Barkalov Alexander, Titarenko Larysa, Mielcarek Kamil

International Journal of Applied Mathematics and Computer Science

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2020

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Vol. 30, no. 4

745--759

EN

Practically, any digital system includes sequential blocks represented using a model of finite state machine (FSM). It is very important to improve such FSM characteristics as the number of logic elements used, operating frequency and consumed energy. The paper proposes a novel technology-dependent design method targeting a decrease in the number of look-up table (LUT) elements and their levels in logic circuits of FPGA-based Mealy FSMs. It produces FSM circuits having three levels of logic blocks. Also, it produces circuits with regular systems of interconnections between the levels of logic. The method is based on dividing the set of internal states into two subsets. Each subset corresponds to a unique part of an FSM circuit. Only a single LUT is required for implementing each function generated by the first part of the circuit. The second part is represented by a multi-level circuit. The proposed method belongs to the group of two-fold state assignment methods. Each internal state is encoded as an element of the set of states and as an element of some of its subsets. A binary state assignment is used for states corresponding to the first part of the FSM circuit. The one-hot assignment is used for states corresponding to the second part. An example of FSM synthesis with the proposed method is shown. The experiments with standard benchmarks are conducted to analyze the efficiency of the proposed method. The results of experiments show that the proposed approach leads to diminishing the number of LUTs in the circuits of rather complex Mealy FSMs having more than 15 internal states. The positive property of this method is a reduction in energy consumption (without any overhead cost) and an increase in operating frequency compared with other investigated methods.

6

The numerical investigation of thin-walled beams with modified C-sections

Grenda M.

Archives of Mechanical Technology and Materials

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2018

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Vol. 38

57--66

EN

Demand for thin-walled structures has been increasing for many years. Cold-formed, thin-walled channel beams are the subject of presented research. The local elastic buckling and limit load of these beams subjected to pure bending are investigated. This study includes numerical investigation called the Finite Strip Method (FSM). The presented results give a deep insight into behaviour of such beams and may be used to validate analytical models. The number of works devoted to the theory of thin-walled structures has been steadily growing in recent years. It means that is an increasing interest in practical methods of manufacturing cold-formed thin-walled beams with complicated cross-sections, including also beams with web stiffeners. The ratio of transverse dimensions of beam to its wall-thickness is high, therefore, thin-walled beams are prone to local buckling that may interact with other buckling modes. The stability constraints should be always considered when using cold-formed thin-walled beams.

7

National-Level Implementation of the Commission Regulation (EU) 2016/631 of 14/04/2016 Establishing a Network Code on Requirements for Grid Connection of Generators

Rychlak J.

Acta Energetica

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2018

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nr 2

4--13

EN

This paper explains the provisions of the network code in the Commission Regulation (EU) 2016/631, known as Network Code Requirements for Generators, and identifies technical and legal conditions related to its implementation at the national level. It specifies, for example, possible concepts of the LFSM automatic control application in the power system defence plan. Based on the National Power System (NPS)’s development scenarios until 2025 and 2030, potential threats to its operation are identified. Issues related to the operation of power system with a high level of wind and PV sources’ penetration are discussed, and the new requirements for generators, which in such conditions are critical for maintaining the power system’s safe operation, are identified.

PL

Artykuł wyjaśnia zapisy kodeksu sieciowego w Rozporządzeniu Komisji (UE) 2016/631, znanym jako Network Code Requirements for Generators, oraz identyfikuje uwarunkowania techniczno-prawne związane z jego implementacją na poziomie krajowym. Podaje przykładowo możliwe koncepcje wykorzystania automatyki LFSM w procesie obrony systemu elektroenergetycznego. Na podstawie scenariuszy rozwoju Krajowego Systemu Elektroenergetycznego (KSE) w perspektywie 2025 i 2030 roku dokonano identyfikacji potencjalnych zagrożeń w jego pracy. Przybliżono zagadnienia związane z funkcjonowaniem systemu elektroenergetycznego, przy wysokim poziomie penetracji generacji wiatrowej i PV, oraz zidentyfikowano nowe wymagania dla wytwórców, które w takich warunkach są krytyczne dla zachowania bezpiecznej pracy systemu elektroenergetycznego.

8

Experimental and numerical (FSM) investigations of thin-walled beams with double-box flanges

Paczos P.

Journal of Theoretical and Applied Mechanics

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2013

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Vol. 51 nr 2

497--504

EN

In the paper, experimental and numerical investigations of thin-walled beams with doublebox flanges were presented. They were a continuation of researches conducted at the Unit of Strength of Materials and Structures at Poznan University of Technology. Numerical results obtained with the Finite Strip Method (FSM) were compared with experimental ones and used for validation of analytical solutions.

PL

W pracy przedstawiono badania doświadczalne i numeryczne belek cienkościennych z półkami skrzynkowymi. Zagadnienie to jest kontynuacją badań przeprowadzonych w Zakładzie Wytrzymałości Materiałów i Konstrukcji Politechniki Poznańskiej. Wyniki numeryczne otrzymane z wykorzystaniem metody pasm skończonych porównano z wynikami uzyskanymi z eksperymentu, a następnie użyto do weryfikacji rozwiązań analitycznych.

9

Finite state machines power dissipation classification

Grześ T.

Zeszyty Naukowe Politechniki Białostockiej. Informatyka

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2012

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Z. 9

31-44

EN

Reduction of the power consumption of digital system can be obtained in many ways. Integrated circuits fabricated in CMOS technology consume power when the state of the output of logic element (gate or ?ip-?op) changes into opposite. Therefore minimizing the number of such changes lead to a reduction of the power consumption. In this paper is presented research of dependence the power dissipation infinite state machines (FSMs) on both probabilities of ones on input lines and probabilities of changes in the input value. The classification scheme for graphs obtained for those dependencies is also proposed. This classification can be used for testing the results of the power reduction process as well as testing the behavior of finite state machine while changing the statistical properties of input signals. Proposed classification can also be used for developing new methods and algorithms of reducing the power dissipation infinite state machines.

PL

Zmniejszenie zużycia energii układu cyfrowego można uzyskać na wiele sposobów. Układy scalone wykonane w technologii CMOS zużywają moc, gdy stan na wyjściu elementu logicznego (bramki lub przerzutnika) zmienia się na przeciwny. Dlatego ´ zmniejszenie liczby takich zmian prowadzi do zmniejszenia zużycia energii. W niniejszym artykule zaprezentowano badania zależności mocy pobieranej przez automat sko ńczony od prawdopodobieństw występowania jedynek logicznych na liniach wejściowych i prawdopodobieństwa zmiany wartości na liniach wejściowych. Zaproponowano również klasyfikację wykresów uzyskanych dla wymienionych zależności. Klasyfikacja ta może być zastosowana do oceny wyników procesu redukcji energii oraz sprawdzenia zachowania automatu skończonego przy zmianie właściwo ści statystycznych sygnałów wejściowych. Zaproponowana klasyfikacja może być również użyta do stworzenia nowych metod i algorytmów zmniejszenia poboru mocy w automatach skończonych.

10

Framework for RIDM within functional safety management process

Barnert T., Kosmowski K., Śliwiński M.

Journal of Polish Safety and Reliability Association

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2012

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Vol. 3, No. 2

217--226

EN

The functional safety management in life cycle is a complex process starting with identifying hazards and defining safety-related functions (SRFs) with regard to the results of risk assessment oriented at determining the safety integrity level of consecutive functions. Another element of such process is a verification of required SIL for considered architectures of safety-related system that implements given safety function. Due to complexity of the problem, to overcome difficulties in safety-related decision making often under considerable uncertainties, usually without taking into account security aspects, we propose to apply the RIDM methodology oriented on functional safety management of programmable control and protection systems in life cycle taking into some more important risk-related factors identified.

11

Synteza blokowa automatów stanów z zastosowaniem łącznego kodowania wielokrotnego

Bukowiec A.

Przegląd Elektrotechniczny

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2011

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R. 87, nr 11

150-153

PL

W artykule zostanie przedstawiona metoda syntezy skończonych automatów stanów z wyjściami typu Mealy'ego do struktur programowalnych. Metoda bazuje na wielokrotnym kodowaniu mikroinstrukcji podzielonych na podzbiory w oparciu o aktualny stan. Dodatkowo podzbiory te są łączone ze sobą w pary tak aby można je było zidentyfikować poprzez wykorzystanie niepełnego kodu. Prowadzi to do realizacji układu cyfrowego automatu z wykorzystaniem struktury dwupoziomowej.

EN

The method of synthesis of Mealy FSMs into FPGAs is proposed. Synthesis is based on the structural decomposition and the multiple encoding. There is proposed an innovation of microinstruction encoding that is called joined multiple encoding. A set of microinstruction is divided into subsets based on a current state. Then, subset are joined into pairs. Each pair is identified base on a part of state code. Next, microinstruction are encoded separately in each pair of subsets.

12

Modelowanie zmiany programu sygnalizacji za pomocą hierarchicznych grafów przejść automatów skończonych

Kawalec P., Krukowicz T.

Logistyka

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2011

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nr 6

PL

Artykuł opisuje zagadnienia związane z modelowaniem zmiany programów sygnalizacji podczas realizacji opisu sterowników sygnalizacji świetlnej za pomocą języków opisu sprzętu. Zawarto w nim zagadnienia wymagań formalnych dla programów przejściowych, zagadnienie określenia liczby programów niezbędnych dla prawidłowego funkcjonowania sterownika oraz weryfikacji poprawności przyjętych założeń. Informacje przedstawione w artykule są oparte na projekcie algorytmu sterowania dla rzeczywistego skrzyżowania.

EN

The paper discribes problems of modelling of changing control program while describing traffic lights controllers with hardware description language. It discusses issues of formal requirements for interchange programs, determination of a number of programs necessary for proper controller operation as well as verification of assumptions. The baseline information for the paper was the design of traffic conrol algorithm for a real road crossing in Warsaw.

13

Statechart-based Controllers Synthesis in FPGA Structures with Embedded Array Blocks

Łabiak G., Borowik G.

International Journal of Electronics and Telecommunications

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2010

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Vol. 56, No. 1

13-24

EN

Statechart diagrams, in general, are visual formalism for description of complex systems behaiour. Digital controllers, which act as reactive systems, can be very conveniently modeled with statecharts and efficiently synthesized in modern programmable devices. The paper presents in details syntax and semantics of statecharts and new implementation scheme. The issue of statecharts synthesis is not still ultimately solved. Main feature of the presented approach is the transformation of statechart diagrams into Finite State Machine, and through KISS format, functional decomposition and mapping into Embedded Memory Blocks. Embedded Memory are part of the modern programmable devices.

14

A graph-based approach to symbolic functional decomposition of finite state machines

Szotkowski P., Rawski M., Selvaraj H.

Systems Science

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2009

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Vol. 35, no 2

41-47

EN

This paper discusses the symbolic functional decomposition method for implementing finite state machines in field-programmable gate array devices. This method is a viable alternative to the presently widespread two-step approaches to the problem, which consist of separate encoding and mapping stages; the proposed method does not have a separate decomposition step - instead, the state's final encoding is introduced gradually on every decomposition iteration. Along with general description of the functional symbolic decomposition method's steps, the paper discusses various algorithms implementing the method and presents an example realisation of the most interesting algorithm. In the end, the paper compares the results obtained using this method on standard benchmark FSMs and shows the advantages of this method over other state-of-the-art solutions.

15

Synthesis of finite state machines for CPLDs

Czerwiński R., Kania D.

International Journal of Applied Mathematics and Computer Science

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2009

|

Vol. 19, no 4

647-659

EN

The paper presents a new two-step approach to FSM synthesis for PAL-based CPLDs that strives to find an optimum fit of an FSM to the structure of the CPLD. The first step, the original state assignment method, includes techniques of two-level minimization and aims at area minimization. The second step, PAL-oriented multi-level optimization, is a search for implicants that can be shared by several functions. It is based on the graph of outputs. Results of experiments prove that the presented approach is especially effective for PAL-based CPLD structures containing a low number of product terms.

16

Wielokrotne kodowanie stanów i mikroinstrukcji automatów implementowanych w strukturach FPGA

Bukowiec A., Barkalov A.

Elektronika : konstrukcje, technologie, zastosowania

|

2009

|

Vol. 50, nr 10

35-37

PL

W artykule przedstawiono metody syntezy skończonych automatów stanów do struktur FPGA z zastosowaniem dekompozycji strukturalnej i wielokrotnego kodowania. Stany automatu oraz mikroinstrukcje są dzielone na podzbiory i kodowane oddzielnie w każdym z nich. Następnie są one dekodowane w układzie drugiego poziomu. Prowadzi to do realizacji układu logicznego automatu w strukturze dwupoziomowej. Rozwiązanie takie zapewnia zbalansowane wykorzystanie dostępnych zasobów sprzętowych, takich jak tablice LUT i osadzone bloki pamięci, w nowoczesnych układach FPGA.

EN

There are presented methods of synthesis of automata into FPGAs with architectural decomposition and multiple encoding in this article. States and microinstructions are divided into subsets and they are encoded separately in each subset. Next, they are decoded in the second level circuit. It leads to realization of logic circuit of automaton in double-level structure. It leads to balanced utilization of available hardware resources, like LUTs and embedded memory blocks, of modern FPGA devices.

17

Structural decomposition of finite state machines

Bukowiec A., Barkalov A.

Electronics and Telecommunications Quarterly

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2009

|

Vol. 55, No 2

243-267

EN

New architectures of FPGA devices combine different type of logic elements like look-up tables, flip-flops and memory blocks. But standard synthesis methods utilize only look-up tables and flip-flops and it makes that device utilization is not optimal one. Methods of synthesis and implementation of Mealy finite state machines into FPGAs there are presented in this article. Synthesis methods are based on the architectural decomposition of logic circuit of FSM and multiple encoding of some its parameters. Architectures of such designed structures are based on existence of decoders as second-level circuits. There is also proposed hardware implementation into FPGAs of developed multi-level structures. The hardware implementation is based on an implementation with use of look-up tables and memory blocks together. The combinational circuit and the register are implemented with use of logic blocks, like in standard realizations. While, decoders are implemented with use of memory blocks. Such realization leads to balanced and rational usage of hardware resources of modern FPGA devices.

18

Improvements to Symbolic Functional Decomposition Algorithms for FSM Implementation in FPGA Devices

Szotkowski P., Rawski M.

Electronics and Telecommunications Quarterly

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2009

|

Vol. 55, No 2

335-354

EN

The method of symbolic functional decomposition for FSM implementation in FPGA devices yields better results than the currently widespread, two-step approaches based on state encoding and mapping of the resulting binary function. This paper presents the method using an example FSM and briefly discusses the existing algorithms, along with results obtained for benchmark FSMs. The paper also proposes a heuristic algorithm for input selection as well as a new, clique-based algorithm for the construction of the crucial decomposition blankets.

19

Realizacja rejestru wyjściowego w układzie cyfrowym automatu z liniowym przekształceniem mikroinstrukcji

Bukowiec A., Barkalov A. A.

Pomiary Automatyka Kontrola

|

2008

|

R. 54, nr 8

565-568

PL

W artykule została omówiona budowa oraz implementacja w strukturze FPGA rejestru wyjściowego w układzie cyfrowym skończonego automatu stanów z wyjściami typu Mealy'ego przy zastosowaniu liniowego przekształcenia mikroinstrukcji. Przy zastosowaniu liniowego przekształcenia mikroinstrukcji wszystkie mikrooperacje wchodzące w skład jednej mikroinstrukcji generowane są szeregowo. W sytuacji gdy nie zaburzy to działania całego systemu może zostać zastosowany rejestr wyjściowy zbudowany z przerzutników typu D, jednak w sytuacji kiedy wymagane jest aby wszystkie mikrooperacje wchodzące w skład jednej mikroinstrukcji generowane były równolegle niezbędne jest zastosowanie specjalnej organizacji rejestru wyjściowego. Zaproponowany w artykule rejestr zapamiętuje kolejne mikrooperacje wchodzące w skład jednej mikroinstrukcji a po załadowaniu ostatniej mikrooperacji wystawia na wyjściu całą mikroinstrukcję. Taki stan wyjść utrzymywany jest aż do momentu całkowitego zapisania kolejnej mikroinstrukcji, która pojawi się na wyjściu dopiero po jej całkowitym zapisaniu w rejestrze. W celu identyfikacji końca mikroinstrukcji wprowadzony jest dodatkowy sygnał, który ustawiany jest jednocześnie wraz z ostatnią mikrooperacją wchodzącą w skład danej mikroinstrukcji.

EN

In this paper, the structure and implementation into FPGA device of output register of digital circuit of finite state machine with Mealy outputs and applied verticalization of microinstructions is described. After verticalization of microinstructions all microoperations from this microinstruction are generated serially. If such manipulation do not affect properly working of whole system there can be applied regular output register be means of D type flip-flops. In the case, when there is required parallel execution of all microoperations there is also required applying of special architecture of output register. The proposed architecture of output register is build up two levels of registers. The register (T type) of first level remember serially generated microoperations from one microinstruction. When whole microinstruction is written into this register then it is stored in the register (D type) of second level. Value of the register of second level is not changed until next microinstruction is fully written. The end of microinstruction is indicated by special additional signal y0. It is generated parallel with last microoperation from particular microinstruction. This signal is used to store whole microinstruction in the register of second level and to reset the register of first level.

20

Kodowanie stanów samokorekcyjnych układów sekwencyjnych

Kania D., Czerwiński R.

Elektronika : konstrukcje, technologie, zastosowania

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2008

|

Vol. 49, nr 5

107-111

PL

Przedstawiono problem kodowania stanów automatów sekwencyjnych w odniesieniu do realizacji tych układów w strukturach programowalnych. Głównym celem jest przedstawienie nowej metody prowadzącej do uzyskiwania struktur samokorekcyjnych. Proponowana metoda jest przedstawiona za pomocą prostej modyfikacji kodowania metodą 1-hot. Wyniki eksperymentów dowodzą, że zaproponowana metoda kodowania prowadzi do istotnej redukcji powierzchni struktury w porównaniu do rozwiązań uzyskiwanych klasyczną metodą kodowania 1-hot.

EN

The paper presents the problem of state assignment for finite state machines (FSM) dedicated to programmable logic devices. The purpose of the paper is to present a new approach to state assignment which provides a self-correcting circuits. The method, based on simple modification of 1-hot method is presented. Results of experiments prove that the proposed state assignment leads to significant reduction of chip area in comparison with the classical 1-hot method.