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PLC implementation in the form of a System-on-a-Chip

Mazur P., Czerwinski R., Chmiel M.

Bulletin of the Polish Academy of Sciences. Technical Sciences

2020

Vol. 68, nr 6

1263--1273

The aim of the paper is to present the implementation of a PLC designed in the form of a System-on-a-Chip. The presented PLC is compatible with the IEC61131‒3 standard. More precisely, the Instruction List language is the native language of the designed CPU, so there is no need for multiple language transformations. In the proposed solution each instruction of the CPU program written in Instruction List is directly translated to machine code. The designed CPU is capable of performing logic operations up to 32-bit Boolean data types. However, the developed CPU is very flexible due to its architecture: data memory can be addressed as bit/byte/word/dword. Moreover, diverse blocks such as timers, counters, and hardware acceleration blocks, can be connected to the CPU by means of an APB AMBA bus. The designed PLC has been implemented in an FPGA device and can be used in cyber-physical systems and Industry 4.0.

Sprzętowa weryfikacja funkcjonalna magistrali AMBA® AXI

Duc P.

Pomiary Automatyka Kontrola

2011

R. 57, nr 8

966-968

W artykule przedstawiono moduł monitora magistrali AMBA® AXI, umożliwiający weryfikację poprawności oraz weryfikację functional coverage protokołu AXI w systemach koemulacji sprzętowo-programowej układów SoC (System-on-Chip). Układ monitora składa się z syntezowalnej części sprzętowej oraz części programowej. Część sprzętowa służy do bezpośredniej obserwacji stanu magistrali i zawiera podstawowe elementy weryfikacyjne, zaś część programowa umożliwia komunikację części sprzętowej z programowym środowiskiem weryfikacyjnym.

The currently observed increase in SoC (System-on-Chip) system complexity determines evolution of the verification methods to ensure complete and as fast as possible verification of the whole system correctness. One of the main direction in development of the complex SoC design verification methodology is implementation of hardware accelerated systems in the verification process. There is a number of ways used in this kind of verification. One is the transaction based hardware-software co-emulation, that support high level software test environment to control and observe the hardware implementation of design under test. This paper presents the AMBA® AXI bus monitor for using in co-emulation systems, with particular attention paid to the Sce-Mi based systems. The monitor architecture has two parts, hardware and software. The synthesizable hardware part is implemented in a programmable device of the emulator system and is used to direct bus observation through basic checkers. The task of the monitor software part is to enable proper configuration of the hardware part, to receive verification status information, to perform more sophisticated checking and to report verification results. Communication between the hardware and software parts is based on exchange of message vectors through a message channel known from the co-emulation Sce-Mi standard.