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A Method to Support Diagnostics of Dynamic Faults in Networks of Interconnections

100%

Garbolino T.

International Journal of Electronics and Telecommunications

2018

tom Vol. 64, No. 3

407--420

The article is devoted to the method facilitating the diagnostics of dynamic faults in networks of interconnection in systems-on-chips. It shows how to reconstruct the erroneous test response sequence coming from the faulty connection based on the set of signatures obtained as a result of multiple compaction of this sequence in the MISR register with programmable feedback. The Chinese reminder theorem is used for this purpose. The article analyzes in detail the various hardware realizations of the discussed method. The testing time associated with each proposed solution was also estimated. Presented method can be used with any type of test sequence and test pattern generator. It is also easily scalable to any number of nets in the network of interconnections. Moreover, it supports finding a trade-off between area overhead and testing time.

Algorytmy i metody dwuprocesorowego sterowania precyzyjnym licznikiem czasu

84%

Sondej T. , Gołaszewski M.

2008

tom Vol. 57, nr 4

309-326

W artykule przedstawiono projekt oprogramowania systemu wieloprocesorowego, składającego się z dwóch procesorów programowych Nios II firmy Altera i precyzyjnego licznika czasu o rozdzielczości około 80 ps. Pierwszy procesor odpowiedzialny jest za komunikację systemu przez interfejs Ethernet z aplikacją uruchamianą na komputerze PC. Drugi procesor steruje licznikiem czasu oraz zajmuje się obliczeniami statystycznymi w czasie wykonywania próby pomiarowej. W artykule przedstawiono również opis projektu sprzętowego oraz problem komunikacji pomiędzy procesorami w systemie wieloprocesorowym.

This paper presents issues of designing and implementing soft ware for multiprocessor systems. Practical example consists of two soft core processors Nios II from Altera. Developed system is designed for control and data processing of precision timer counter with 80-ps resolution. The first processor runs as a server, providing communication and supervision of the system via the Internet. The second processor controls timer counter and performs statistical computation. Shared memory from FPGA resources is used to interchange data between processors.

Pipelined pseudo-random number generator with the efficient post-processing method

84%

Dąbal P.

tom Vol. 6, nr 2

43--48

This brief proposes a novel architecture of the chaotic pseudo-random bit generators (PRBGs) based on the chaotic nonlinear model and pipelined data processing. We investigated PRBG built on the chaotic logistic map and frequency dependent negative resistances (FDNR). A significant enhancement in terms of output throughput has been achieved by combining the advantages of pipelining with post-processing based on fast logical operations like bit shifting and XOR. The proposed method has been implemented using programmable SoC Zynq device from Xilinx. We verified output pseudo-random bit stream by standard statistical tests NIST SP800-22. We also present detailed comparison of the proposed post-processing method with the methods reported previously by the other authors. In particular, we compared the maximum output throughput and amount of total logical resources required by PRBG implementation in the programmable SoC device. For PRBGs based on the logistic chaotic map and frequency dependent negative resistance (FDNR) we obtained speed-up factors equal to 33% and 14%, respectively. By composing the output stream of 3 data channels in PRBG with FDNR element, we get the maximum throughput equal to 38.43 Gbps. That is significantly greater comparing to the chaotic PRBGs described so far.

A Method to Support Diagnostics of Dynamic Faults in Networks of Interconnections

84%

Garbolino T.

tom 64

nr 3

Testbed for thermal and performance analysis in MPSoC systems

67%

Sojka M. , Benedikt O. , Hanzálek Z. , Zaykov P.

tom Vol. 21

683--692

Many modern computing platforms in the safety-critical domains are based on heterogeneous Multiprocessor System-on-Chip (MPSoC). Such computing platforms are expected to guarantee high-performance within a strict thermal envelope. This paper introduces a testbed for thermal and performance analysis. The testbed allows the users to develop advanced scheduling and resource allocation techniques aiming at finding an optimal trade-off between the peak temperature and the achieved performance. This paper presents a new, open-source Thermobench tool for data collection and analysis of user-defined workloads. Furthermore, a methodology for shortening the time needed for the data collection is proposed. Experiments show that a significant amount of time can be saved. Specifically, time reduction from 60 minutes to 15 minutes is achieved with the i.MX8 MPSoC from NXP while running a set of user-defined benchmarks that stress CPU, GPU, and different levels of the memory hierarchy.