Wyniki wyszukiwania - Biblioteka Nauki

1

Digital random bit generators implemented in FPGAs offered by various manufacturers

100%

Kubczak P. , Matuszewski Ł. , Jessa M. , Łoza S.

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2015

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tom Vol. 61, No. 7

293--295

EN

In cryptography, we require that a random sequence should have excellent statistical properties as well as non-deterministic character. Combining multiple independent sources of randomness using the modulo two operation, significantly improves the statistical properties of the generated sequences and also affects the accumulation of true randomness generated in the oscillator sources. This is a very promising method of producing random sequences. In this paper, we compare the implementations of the RO-based combined random generator in various FPGAs technologies offered by various manufactures (Xilinx, Altera, Lattice). In this research, we used a NIST 800-22 statistical test suite to assess the statistical properties. The results show that the method of producing strings with a combined generator is the method stable in terms of technology. The results are similar for implementation in all FPGA used in the experiment. So, the proposed generator can be implemented in various programmable structures together with other components of a cryptographic system.

2

A proposal of output speed multiplication technique for true random number generators based on ring oscillators

88%

Matuszewski Ł. , Kubczak P.

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tom Vol. 62, No. 5

157--159

EN

Nowadays modern cryptographic systems require a tremendous amount of keys. Very fast random number generators (RNGs) are needed to produce those keys in the requested time, but what to do when a solution that is already in use reaches the maximum speed? The aim of the paper is to find the answer to this question. In addition, generated random numbers should not leave a cryptographic system, because according to the Kerckhoffs thesis, the security of the whole system should be based only on a key. The cryptographic system should be enclosed within a single chip. In order to check new ideas and prove them, there were used NIST 800-22 test suite and restarts mechanism. The basic concept of the generator built of ring oscillators is still the same; ring oscillators are combined by XOR gates tree. A single ring oscillator consists of inverter, latch and NAND. This kind of construction provides a tool to make synchronous start and stop of all oscillators and the restart mechanism technique is applied in this manner. The speed of generation was increased by using multiple parallel generator trees to generate instantly the whole n-bit word. The paper shows that reproduction of the base structure is not a simple method of increasing the speed of generator. Moreover, it is always important to carefully consider all new ideas, because even if the NIST statistical test suite is passed, there is a chance that the restart mechanism will show some correlations that can be used during attack on the system.

3

Evaluation of Selected Timing Parameters of FPGA Device

75%

Sondej D. , Szymanowski R. , Szplet R.

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2018

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tom Vol. 64, No. 1

23--25

EN

We present a method and results of measurements of FPGA (Field Programmable Gate Array) selected timing parameters crucial in many timing sensitive applications such as precise time and frequency metrology. Two main parameters, i.e. the delay and its jitter, were evaluated for look-up-tables (delay 740 ps/jitter 1.33 ps), IO buffers (na/0.45 ps) and carry-chain multiplexers (28ps/0.153 ps) integrated in a programmable device Spartan-6 (Xilinx) which is one of most popular FPGA chips on the market now. Measurements were performed with the use of fast real-time sampling oscilloscope.

4

Mikrokomputer Raspberry Pi jako sterownik systemu pomiarowego

75%

Michalak S.

Pomiary Automatyka Kontrola

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2014

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tom R. 60, nr 8

649--651

PL

W artykule przedstawiono system pomiarowy, w którym nadrzędną rolę sprawuje mały, cieszący się coraz większą popularnością, mikrokomputer edukacyjny Raspberry Pi. System zaprojektowany został do wizualizacji rozkładu temperatury wewnątrz struktury układu reprogramowalnego FPGA, na podstawie dokonanych pomiarów częstotliwości oscylatorów pierścieniowych zaimplementowanych wewnątrz układu. Sterowanie procesem pomiarowym, akwizycja danych i prezentacja wyników nadzorowana jest przez mikrokomputer Raspberry Pi.

EN

In this paper the system based on Raspberry Pi, a popular educational microcomputer [1] is described. In this system, a programmable FPGA Spartan-3 XC3S200 [5] device was tested. The Raspberry Pi worked as a control unit for the whole system (Fig. 1). A part of the system was implemented inside the tested structure (Fig. 2). It was an array of ring oscillators (Fig. 3), as temperature sensors, with a structure for controlling the ring oscillators. Simple ring oscillators are often implemented in FPGA devices. They are used both as a single element or an array of sensors for measuring the chip temperature [2, 3, 4]. The frequency of the activated sensor was measured outside by an oscilloscope (SCPI command was used). The frequency was dependent on temperature. The sensors can be located in different areas of a chip [6, 7]. In case of the tested device 36 sensors were used, but generally it depends on a tested device [8, 9]. The Raspberry Pi controlled the measurement process via an SPI serial interface. The results were collected from the oscilloscope via a UART/RS232 serial interface. The relation between frequency and temperature (Fig. 4) as well as 2D visualizations (Fig. 5) were made using Gnuplot and Scilab. The results should visualize the temperature distribution inside the device, but first right calibration of sensors should be made. The location of elements inside the FPGA sensor is of great significance [10], so in the case of an array of sensors, each ring oscillator should be analyzed and calibrated independently.

5

A digital true random number generator implemented in different Xilinx FPGAs

63%

Matuszewski Ł. , Jessa M.

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2013

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tom R. 59, nr 8

742--744

EN

In cryptography we often require sequences of numbers with unpredictable elements. Such sequences cannot be produced by purely deterministic systems. A novel method for producing true randomness and increasing the randomness of a combined TRNG using ring oscillators is described. In this paper we show that the proposed method provides similar results for generators implemented using different technologies offered by Xilinx. Thus, the proposed generator can be implemented in different FPGAs with other elements of a cryptographic system.

PL

W kryptografii często wymaga się ciągów liczb złożonych z nieprzewidywalnych elementów. Takie sekwencje nie mogą być wytwarzane w systemach czysto deterministycznych. Inżynierowie muszą opracować źródła losowości, których właściwości muszą być ocenione i potwierdzone przez niezależne badania, przynajmniej doświadczalnie. W artykule pokazano, że proponowana metoda wytwarzania losowości jest stabilna pod względem technologicznym. Uzyskano bardzo zbliżone rezultaty dla generatorów losowych zrealizowanych w strukturach FPGA (Field Programmable Gate Array) wykonanych w różnych technologiach jakie oferuje firma Xilinx. W żadnym przypadku nie korzystano z manualnego rozmieszczania elementów w matrycy FPGA, aby uzyskać lepsze rezultaty. Położenie poszczególnych składników zależało tylko od oprogramowania dostarczanego przez producenta. Zatem proponowany generator może być implementowany w różnych układach FPGA razem z innymi elementami systemu kryptograficznego.

6

Low-power wide-frequency-range ring oscillator for temperature-controlled oscillator

63%

Frankiewicz M. , Kos A.

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2013

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tom Vol. 54, nr 12

25-27

EN

The paper describes structure and simulation results of the novel ring oscillator designed in UMC CMOS 0.18 μm (1.8 V) which is a part of power management system including Temperature-Controlled Oscillator. Frequency generated by the oscillator is tuned by scaling the supply voltage, additionally ring length is digitally controlled. Presented ring oscillator has very wide tuning range (250 MHz–2.1 GHz) with small current consumption (34–689 μA).

PL

Artykuł opisuje strukturę i wyniki symulacji oscylatora pierścieniowego zaprojektowanego w technologii UMC CMOS 0,18 μm (1,8 V), który jest częścią systemu zarządzania mocą układu scalonego zawierającego generator przestrajany temperaturą układu. Częstotliwość generowana przez oscylator jest przestrajana poprzez zmianę napięcia zasilania, dodatkowo długość pierścienia oscylatora jest kontrolowana sygnałem cyfrowym. Opisywany oscylator ma bardzo szeroki zakres przestrajania (250 MHz–2,1 GHz) przy niskim poborze prądu (34–689 μA).

7

Realization of logic integrated circuits in VeSTIC process - design, fabrication, and characterization

51%

Domański K. , Głuszko G. , Sierakowski A. , Tomaszewski D. , Szmigiel D.

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tom Vol. 9, nr 3

123--132

EN

A design and manufacturing of test structures for characterization of logic integrated circuits in a VeSTIC process developed in ITE, are described. Two variants of the VeSTIC processs have been described. A role and sources of the process variability have been discussed. The VeSFET I-V characteristics, the logic cell static characteristics, and waveforms of the 53-stage ring oscillator are presented. Basic parameters of the VeSFETs have been determined. The role of the process variability and of the parasitic elements introduced by the conservative circuit design, e.g. wide conductive lines connecting the devices in the circuits, have been discussed. Based on the inverter layout and on the process specification, the parasitic elements of the inverter equivalent circuit have been extracted. The inverter propagation times, the ring oscillator frequency, and their dependence on the supply bias have been determined.

8

Niskomocowy generator pierścieniowy CMOS sterowany napięciem

51%

Mroszczyk P. , Gołda A. , Kos A.

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2010

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tom Vol. 51, nr 9

11-14

PL

W pracy przedstawiono projekt i wyniki symulacji po ekstrakcji z topografii generatora pierścieniowego wykonanego w technologii AMS 0,35 pm przestrajanego w zakresie od 50 kHz do 2 GHz, moc strat nie przekracza 5,3 mW przy napięciu zasilania 3,3 V, poziom szumów fazowych dla częstotliwości podstawowej 900 MHz i przesunięciu 1 MHz wynosi -87,4 dBc/Hz, głównym przeznaczeniem układu jest taktowanie systemów cyfrowych testowanych pod kątem zjawisk termicznych i elektrotermicznych

EN

The objective of this paper is to present a design and post-layout simulation results of a voltage-controlled ring oscillator designed in AMS 0.35 pm technology retuned from 50 kHz to 2 GHz. A power dissipation does not exceed 5.3 mW for a voltage supply 3.3 V, a single-sideband noise at the offset frequency 1 MHz from the carrier frequency 900 MHz is - 87.4 dBc/Hz. The project can be applied as a clock signal generator in research and development of digital systems in terms of thermal and electrothermal phenomena