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WWW-based Boolean function minimization

100%

Tomaszewski S. P. , Celik I. U. , Antoniou G. E.

nr 4

577-583

In this paper a Boolean minimization algorithm is considered and implemented as an applet in Java. The application is based on the Quine-McCluskey simplification technique with some modifications. The given application can be accessed on line since it is posted on the World Wide Web (WWW), with up to four variables, at the URL http://www.csam.montclair.edu/~antoniou/bs. After extensive testing, the performance of the algorithm has been found to be excellent. The proposed application is a useful aid for students and professors in the fields of electrical and computer engineering and computer science as well as a valuable tool for digital designers.

Structured Mapping of Petri Net States and Events for FPGA Implementations

72%

Tkacz J. , Adamski M.

tom Vol. 59, No. 4

331-339

The paper presents a new method of structured encoding of global internal states and events in Reconfigurable Logic Controllers, which are directly mapped into Field Programmable Gate Arrays (FPGA). Modular, concurrently decomposed, colored state machine is chosen as a intermediate model, before the mapping of Petri net into an array structure of dedicated but very flexible and reliable digital system. The initial textual specification in formal Gentzen logic serves both as a design description for a rapid prototyping, as well as formal model, suitable for detailed computer-based reasoning about optimized and synthesized logic controller, implemented in configurable hardware. Only the selected linear subset from general, universal propositional Gentzen Logic is necessary to deduce several properties of the net, such as relations of nonconcurrency among structurally ordered macroplaces. The goal of this paper is to present the design methodology for modeling and synthesis of discrete controllers using related Petri net theory, rule-based theory (mathematical logic), and VHDL.

Synthesis of logic circuits for FPGA

58%

Plushch Y. , Chemeris A. , Reznikova S.

tom Vol. 48, nr 7

25-27

The method of synthesis of discrete devices is considered in the present paper. The method generates the description of the device with matrix srtucture in the elements base {AND, NOT, ADDER} on the bases of analytical and tabular forms of functional relationships. The practical realization of the algorithm that generates VHDL device description is given and examples are demonstrated.

W artykule rozpatruje się metodę syntezy urządzeń logicznych. Metoda ta generuje opisy urządzenia o strukturze macierzowej składającego się z elementów typu {AND, NOT, ADDER} na podstawie funkcjonalnych zależności analitycznych oraz tabularycznych. Przedstawiono przykłady i algorytm do generowania opisów urządzenia w języku VHDL.