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EN
We summarize recent results on polarization-bistable vertical-cavity surface-emitting lasers (VCSELs) and their application to optical buffer memory. All-optical flip-flop operation with very low switching energies and high repetition rates is achieved. An optical buffer memory consisting of a two-dimensional array of polarization-bistable VCSELs, in which the bit state of the optical signal, ''0'' or ''1'', is stored as a lasing linear polarization state of 0 or 90°. Input data stored as the polarization states of the first VCSEL are transferred to the polarization states of the second VCSEL. In our experiments with 980 nm polarization-bistable VCSELs, 10 Gbit/s optical buffering, 2-bit optical buffering, and a shift register function have been successfully demonstrated.
2
Content available remote Design for reliability: delay faults modeling and simulation for CMOS flip-flops
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EN
Continuously scaling down of CMOS technology brings on low power but also reliability problems such as aggravated aging effects and process variations. They can influence and degrade the performance of integrated circuits. In recent years, reliability issues of 65nm CMOS node has been intensively studied. In this work, a reliability assessment approach considering aging mechanisms and parametric process variation induced delay fault is proposed in design loop. Negative bias temperature instability (NBTI) and hot carrier injection (HCI) induced degradation are simulated in 65nm flip-flops with different architectures. An example with simple combinational logic (65nm full adder) illustrates this approach for fault probability. It is concluded that process variations are more important comparing to aging effects induced degradation when designing low power digital flip-flops.
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