Wyniki wyszukiwania - Biblioteka Nauki

Nowa wersja platformy, zawierająca wyłącznie zasoby pełnotekstowe, jest już dostępna.
Przejdź na https://bibliotekanauki.pl

Ograniczanie wyników

Znaleziono wyników: 2

Liczba wyników na stronie

Wyniki wyszukiwania

Wyszukiwano:
w słowach kluczowych: filtr adaptacyjny

Sortuj według:

Ogranicz wyniki do:

Noise Reduction in High Resolution ECG by Using Frequency-domain Adaptive Filtering

100%

Cytowski J.

tom Vol. 9

25--29

In this paper a frequency-domain least-mean-square adaptive filter (FDLMS) is used to cancel noise in real time recording of the high resolution ECG (HRECG). In this paper, beside the classical FDLMS solutions, an application of the network of the time sequenced adaptive recurrent filter is shown. Such a filter requires of an additional synchronisatian algorithm, however, is able to tract rapidly varying nonstationarities without smoothing effect and therefore can be used for dynamically changing ECG signals. The results of our experiment show the importance of using digital signal processing when dealing with HRECG signal corrupted by noise.

Novel hardware-efficient design of LMS-based adaptive FIR filter utilizing Finite State Machine and Block-RAM

84%

Sharifi-Tehrani O.

Przegląd Elektrotechniczny

2011

tom R. 87, nr 7

240-244

A novel pure-hardware design of LMS-based adaptive FIR filter core is proposed which is highly efficient in FPGA area/resource utilization and speed. Unlike HW/SW co-design and other pure-hardware methods, the required area/resource is reduced while keeping the speed in an appropriate level by taking advantage of finite state machine (FSM) and using internal block-rams (BRAM). This model because of being completely general (device independent), gives the ability of implementation on different FPGA brands and thus, is suitable for embedded systems, system-onprogrammable- chip (SoPC) and network-on-chip (NoC) applications.

Opisano projekt filtru adapatacyjnego SOI który może byc wykorzystany w technice FPGA. Dla zapewnienia odpowiedniej szybkości zastosowano metodę FSM (finite state machine) i wewnętrzny RAM. Układ może być wykorzystany w systemach typu SoPC (system on programmable chip).