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The low-area FPGA design for the post-quantum cryptography proposal Round5

100%

Andrzejczak M.

2019

tom Vol. 18

213--219

Post-Quantum Cryptography (PQC) is getting attention recently. The main reason of this situation is the announcement by the U.S. National Institute for Standard and Technology (NIST) about an opening of the standardization process for PQC. Recently NIST published a list of submissions qualified to the second round of this process. One of the selected algorithms is Round5, offering a key encapsulation mechanism (KEM) and public key encryption (PKE). Due to high complexity of post-quantum cryptosystems, only a few FPGA implementations have been reported to date. In this paper, we report results for low-area purely-hardware implementation of Round5 targeting low-cost FPGAs.

Calibration of a mixed-signal power network transient stability analysis emulator

67%

Lanz G. , Fabre L. , Lilis G. , Kyriakidis T. , Sallin D. , Cherkaoui R. , Kayal M.

tom Vol. 4, nr 4

142--147

The emerging ﬁeld of power system emulation for real time smart grid management is very demanding in terms of speed and accuracy. This paper provides detailed information about the electronics calibration process of a high-speed power network emulator dedicated to the transient stability analysis of power systems. This emulator uses mixed-signal hardware to model the dynamic behavior of a power network. Special design allows the self-calibration of the analog electronics through successive measurements and correction steps. The calibration operation guarantees high resolution of the transient stability analysis results, so that they can be reliably used for operational planning and control on real power networks.

Comparison of three different 2-D space vector PWM algorithms and their FPGA implementations

67%

Bishuang F. , Guanzheng T. , Shaosheng F.

tom Vol. 94, nr 3

176--189

To improve the flexibility of the multilevel space vector pulse width modulation (SVPWM), various algorithms have been developed. A theoretical comparison is made for three 2-D SVPWM algorithms: they are g-h frame, α' - β' frame and multilevel SVPWM based on two-level (α* - β* frame). The aim is to provide a guideline for the selection of the most appropriate SVPWM technique for digital implementation. Among them, the α' - β' frame offers the best flexibility with the least calculation and is well suited for digital implementation. The α* - β* frame is the most intuitionistic but has the largest calculation. New general methods of the g-h frame and α' - β' frame for any level SVPWM are also provided, which needs only the angle θ and the modulation depth m to generate and arrange the final vector sequence. All three methods are implemented in a field programmable gate array (FPGA) with very high speed integrated circuit hardware description language (VHDL) and compared in terms of implementation complexity and logic resources required. Simulation results show the absolute advantages of α' - β' frame in briefness and resources use. Finally, an experimental test result is presented with a three-level neutral-point-clamped (NPC) inverter.