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1 International Journal of Microelectronics and Computer Science

1 2014

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Design for reliability: delay faults modeling and simulation for CMOS flip-flops

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Cai H. , Liu K. , An T. , Naviner L.

International Journal of Microelectronics and Computer Science

2014

tom Vol. 5, nr 3

98--104

Continuously scaling down of CMOS technology brings on low power but also reliability problems such as aggravated aging effects and process variations. They can inﬂuence and degrade the performance of integrated circuits. In recent years, reliability issues of 65nm CMOS node has been intensively studied. In this work, a reliability assessment approach considering aging mechanisms and parametric process variation induced delay fault is proposed in design loop. Negative bias temperature instability (NBTI) and hot carrier injection (HCI) induced degradation are simulated in 65nm ﬂip-ﬂops with different architectures. An example with simple combinational logic (65nm full adder) illustrates this approach for fault probability. It is concluded that process variations are more important comparing to aging effects induced degradation when designing low power digital ﬂip-ﬂops.