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EN
In this paper MIS equivalent electrical circuit of Au/Pd/Ti–SiO2–GaAs has been analyzed by a comparison of the results obtained from admittance and DLTS spectroscopy. Two groups of peaks with different magnitude and different gate voltage dependence have been observed in DLTS and admittance spectra. Based on the analysis of the peaks behavior, it has been concluded that they are associated with the response of bulk traps and interface states, respectively. In order to characterize bulk traps and interface states responsible for the occurrence of two groups of peaks in normalized conductance spectra we have used the equivalent circuit with two CPE-R branches. The time constant values estimated for both peaks from admittance analysis have been compared with the time constant determined from DLTS analysis. Some discrepancies have been noted between the time constants obtained for interface states whereas the time constants for bulk traps were compatible. It has been also demonstrated that when conductance peaks overlap, the admittance experimental data can be fitted by the equivalent electrical model with only one CPE-R branch. However, in this case incomplete information about the analyzed process has been obtained despite the fact that all model validity criteria can be fulfilled and the model seems to be correct.
PL
W pracy przedstawiono nową, szybką metodę pomiaru przekrojów czynnych pułapek powierzchniowych, wykorzystującą mapę konduktancji w graficznej analizie pułapek MPAS. Przy użyciu tej metody określono przekroje czynne pułapek w próbkach SiC-3C z tlenkiem bramkowym SiO2 wytwarzanym dwiema metodami (PECVD i mokre utlenianie termiczne 3C-SiC) i z różnymi materiałami bramki (AI, Au, Ni i poli-Si). Uzyskane wyniki wskazują, że pułapki w większości próbek mają typowe wartości przekroju czynnego on ok. 10-15 cm2, charakterystyczne dla centrów Pb. Większe przekroje czynne stwierdzono jedynie w próbkach WET/Ni (on ok. 10-13 cm2), ale wyjaśnienie przyczyny tego odchylenia wymaga dalszych badań.
EN
The MPAS maps are a new, convenient and fast method of interface trap characterization. Using the same data as measured by the conductance method, the MPAS technique requires much less computational effort, allowing for graphical analysis of the distributions of traps in the space of energy position vs. trapping speed, and enabling direct evaluation of trap density and capture cross-section. The graphical method of trap capture cross-section evaluation is proposed based on MPAS. A grid made of lines is calculated for a sequence of capture cross-section values, and superimposed on the MPAS maps. The straight ridge formed by measured conductance In(Gm/ω) in (fs, In(ω-1)) coordinates aligns well with the grid lines, what enables the evaluation of trap capture cross-sections in the constant on range by matching the nearest on line with the In(Gm/ω) ridge line. Using this method, a set of samples of SiC-3C based MOS capacitors with different oxide preparation technology and different gate materials was analyzed and only small deviations from on=10-15 cm2 were detected. As that is the typical trap size of the commonly found Pb - centres, we concluded that the trap centres observed on the MPAS maps in this experiment were mainly, although not exclusively, the dangling bonds.
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