In computational biology the development of algorithms for the identification of tandem repeats in DNA sequences is a challenging problem. Tandem repeats identification is helpful in gene annotation, forensics, and the study of human evolution. In this work a signal processing algorithm based on adaptive S-transform, with Kaiser window, has been proposed for the exact and approximate tandem repeats detection. Usage of Kaiser window helped in identifying short as well as long tandem repeats. Thus, the limitation of earlier S-transform based algorithm that identified only microsatellites has been alleviated by this more versatile algorithm. The superiority of this algorithm has been established by comparative simulation studies with other reported methods.
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An active noise control (ANC) system utilizing a genetic algorithm for reduction of noise in duct is described. A continuous genetic algorithm with a heuristic crossover method was applied in the controller of the system. The ANC system was tested on a laboratory stand. Measurements of the efficiency of the system related to basic parameters of the genetic algorithm were performed. A comparison of the effectiveness of ANC system based on the genetic algorithm to the system based on the LMS algorithm is presented.
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In this paper, efficient pipelined architectures for Least Mean Square (LMS) adaptive filtering and system identification of discrete-time Volterra models is presented. First, the multichannel embedding is adopted for the transformation of the discrete-time Volterra model to an equivalent multi-input single output format. Then, the LMS algorithm with delayed coefficients adaptation is applied, for the identification of the model parameters. The adaptation delay introduced in the computational flow of the adaptive scheme, allows for a pipelined implementation, however, the convergence and tracking properties of the algorithm are affected. Proper correction terms are subsequently introduced that compensate the adaptation delay and give results identical to the original LMS algorithm, subject to a latency delay.
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Active Noise Control (ANC) has become an important field of research in recent decades. Noise Control in industrial environments and conference halls as well as in communication systems has been studied under the title adaptive-active noise cancellation-control (AANCC) and the results of these studies have been used in practical applications. Reducing time dependent noise is one of the ways recommended for speech enhancement. Here we have introduced an artificial neural network called ADALINE as a smart dual microphone active noise control system. This artificial neural network identifies sources of noise and interference during its training phase and adjusts accordingly. In this way the system reduces the input signal noise. Tests and implementations presented here are based on speech in Persian language and cumulative white Gaussian noise and the interference is assumed to be of the cosine type.
PL
Przedstawiono analizę szumów w otoczeniu przemysłowym i w salach konferencyjnych a następnie przedstawiono metody adaptacyjnych metod redukcji szumów. Szczególną uwagę zwrócono na szum zależny od czasu. Zastosowano metodę podwójnego mikrofonu i wykorzystano sieci neuronowe. Sieć identyfikuje źródło szumu i zakłóceń. Metodę sprawdzono doświadczalnie.
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A novel pure-hardware design of LMS-based adaptive FIR filter core is proposed which is highly efficient in FPGA area/resource utilization and speed. Unlike HW/SW co-design and other pure-hardware methods, the required area/resource is reduced while keeping the speed in an appropriate level by taking advantage of finite state machine (FSM) and using internal block-rams (BRAM). This model because of being completely general (device independent), gives the ability of implementation on different FPGA brands and thus, is suitable for embedded systems, system-onprogrammable- chip (SoPC) and network-on-chip (NoC) applications.
PL
Opisano projekt filtru adapatacyjnego SOI który może byc wykorzystany w technice FPGA. Dla zapewnienia odpowiedniej szybkości zastosowano metodę FSM (finite state machine) i wewnętrzny RAM. Układ może być wykorzystany w systemach typu SoPC (system on programmable chip).
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