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1
Content available remote Hopf bifurcations in a three-species food chain system with multiple delays
100%
Open Mathematics
|
2017
|
tom 15
|
nr 1
508-519
EN
This paper is concerned with a three-species Lotka-Volterra food chain system with multiple delays. By linearizing the system at the positive equilibrium and analyzing the associated characteristic equation, the stability of the positive equilibrium and existence of Hopf bifurcations are investigated. Furthermore, the direction of bifurcations and the stability of bifurcating periodic solutions are determined by the normal form theory and the center manifold theorem for functional differential equations. Finally, some numerical simulations are carried out for illustrating the theoretical results.
Open Mathematics
|
2017
|
tom 15
|
nr 1
218-232
EN
This paper is concerned with a competition and cooperation model of two enterprises with multiple delays and feedback controls. With the aid of the difference inequality theory, we have obtained some sufficient conditions which guarantee the permanence of the model. Under a suitable condition, we prove that the system has global stable periodic solution. The paper ends with brief conclusions.
3
86%
EN
Globally positive solutions for the third order differential equation with the damping term and delay, $$ x''' + q(t)x'(t) - r(t)f(x(\phi (t))) = 0, $$ are studied in the case where the corresponding second order differential equation $$ y'' + q(t)y = 0 $$ is oscillatory. Necessary and sufficient conditions for all nonoscillatory solutions of (*) to be unbounded are given. Furthermore, oscillation criteria ensuring that any solution is either oscillatory or unbounded together with its first and second derivatives are presented. The comparison of results with those in the case when (**) is nonoscillatory is given, as well.
4
Content available remote Existence of solutions for delay evolution equations with nonlocal conditions
86%
Open Mathematics
|
2017
|
tom 15
|
nr 1
616-627
EN
In this paper, we are devoted to study the existence of mild solutions for delay evolution equations with nonlocal conditions. By using tools involving the Kuratowski measure of noncompactness and fixed point theory, we establish some existence results of mild solutions without the assumption of compactness on the associated semigroup. Our results improve and generalize some related conclusions on this issue. Moreover, we present an example to illustrate the application of the main results.
5
Content available remote Performance Enhancement Heterogeneous Based EECP for Bandwidth Utilization
86%
EN
Using the increase of user made on distributed network scheme, traffic congestion is one of the necessary circumstances. Distributed network consists of various networks, processors and intermediary strategies that overwork the changes or routers with high traffic and it is because of the project fault in the circulated networking architecture. Even though several researchers address the congestion recognition method, its avoidance and modification in their investigation are solid to be explored for any effective solution for this problem. Due to huge network congestion user will face the network speed problem, real congestion control methods are desirable, and mainly to solve``bursty'' transportation of today's for actual extraordinary speed networks. Subsequently dawn 90's many systems have been proposed. This paper concentrates on heterogeneity based congestion mechanism patterns on the basis of certain key performance metrics. Mainly in this work we will judge the performance of Delay, congestion rate, throughput and channel capacity EECP based solution for a steady state against these key performance metrics.
EN
Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.
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