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Transresistance CMOS neuron for adaptive neural networks implemented in hardware

100%

Wojtyna R. , Talaśka T.

tom Vol. 54, nr 4

443-448

A simple analog circuit is presented which can play a neuron role in static-model-based neural networks implemented in the form of au integrated circuit. Operating in a transresistance mode it is suited to cooperate with transconductance synapses. As a result, its input signal is a current which is a sum of currents coming from the synapses. Summation of the currents is realized in a made at the neuron input. The circuit bas two outputs and provides a step function signal at one output and a linear function one at the other. Activation threshold of the step output can be conveniently controlled by means of a voltage. Having two outputs, the neuron is attractive to be used in networks taking advantage of fuzzy logic. It is built of only five MOS transistors, can operate with very law supply voltages, consumes a very law power when processing the input signals, and no power in the absence of input signals. Simulation as well as experimental results are shown to be in a good agreement with theoretical predictions. The presented results concern a 0.35 [mi]m CMOS process and a prototype fabricated in the framework of Europractice.

Fully Analytical Characterization of the Series Inductance of Tapered Integrated Inductors

86%

Passos F. , Fino M. H. , Moreno E. R.

tom Vol. 60, No. 1

73-77

In this paper a general method for the determination of the series inductance of polygonal tapered inductor s is presented. The value obtained can be integrated into any integrated inductor lumped element model, thus granting the overall characterization of the device and the evaluation of performance parameters such as the quality factor or the resonance frequency. In this work, the inductor is divided into several segments and the corresponding self and mutual inductances are calculated. In the end, results obtained for several working examples are compared against electromagnetic (EM) simulations are performed in order to check the validity of the model for square, hexagonal, octagonal and tapered inductors. The proposed method depends exclusively on the geometric characteristics of the inductor as well as the technological parameters. This allows its straight forward application to any inductor shape or technology.

Cascode ampliﬁers with low-gain variability and gain enhancement using a body-biasing technique

72%

Pereira N. , Oliveira L. B. , Goes J. , Oliveira J. P.

2013

tom Vol. 4, nr 3

98--102

This paper presents a simple circuit technique to reduce gain variability with PVT variations in cascode ampliﬁers using a body-biasing scheme, while enhancing the overall gain of the ampliﬁer. Simulation results of a standard telescopic-cascode ampliﬁer, in two different nanoscale CMOS technologies (130 nm and 65 nm) show that the proposed compensated circuit ampliﬁer exhibits a (DC) gain variability smaller (below ± 0.5 dB) than the original (uncompensated) circuit, while reaching a gain enhancement of about 3 dB. The required auxiliary biasing circuit dissipates around 5% of the main ampliﬁer circuit.