Wyniki wyszukiwania - Biblioteka Nauki

1

Modelowanie i weryfikacja złożonych układów cyfrowych z wykorzystaniem środowiska MATLAB i Simulink

100%

Milik A.

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tom R. 54, nr 8

569-571

PL

Artykuł przedstawia metodę połączenia środowiska modelowania matematycznego MATLAB oraz Simulink ze środowiskiem przeznaczonym do modelowania systemów cyfrowych opartym na symulatorze zgodnym z normami języków Verilog i VHDL. Zaproponowane rozwiązania umożliwiają łatwą weryfikację i projektowanie urządzeń cyfrowych z wykorzystaniem podejścia algorytmicznego.

EN

The paper presents methodologies of interfacing a standard HDL simulation environment to MATLAB and Simulink environments. Two co-simulation environments are considered for MATLAB and Simulink respectively. There are several factors that must be resolved before smooth and efficient cosimulation is possible. In case of complex circuits performance is extremely important factor. There are considered problems of time synchronization, data conversion and communication between two different simulation environments. As simulator kernels are inaccessible for modification the optimization can only be introduced to linking library.

2

Samorekonfigurowalny system cyfrowy

63%

Milik A. , Mocha J.

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tom R. 54, nr 8

483-485

PL

W artykule przedstawiono propozycję sprzętowej platformy samorekonfigurowalnej, implementowanej w układzie FPGA. Aby ułatwić zarządzanie konfiguracjami, został zaprojektowany niewielki rdzeń układu, pozwalający na szybką podmianę fragmentu konfiguracji układu. W celu ułatwienia procesu projektowania układów samorekonfigurowalnych, zaproponowano narzędzie przeznaczone do tworzenia projektu oraz generacji szkieletu modułów, jak i skryptów do przetwarzania wsadowego projektu.

EN

The paper propose the selfreconfigurable hardware platform implemented in an FPGA (Spar-tan II/ Spartan 3). The key factor of the design is hardware configuration manager. This is carefully designed small hardware core that manages system configuration. Based on request and configuration registration table it finds partial configuration bit stream start address in external memory and transfers it through SelectMAP interface. In the same it asserts internal BUSY signal until reconfiguration is completed and newly created circuit is properly initialized. There is also presented wizard for partial reconfiguration design flow. It allow to create design skeleton from signal definitions and their assignments between static and dynamic part of the design. Wizard automatically inserts configuration manager core. All those improvements allow to concentrate on implementing functionality instead of taking care of design processing details.

3

Synthesis and Implementation of Reconfigurable PLC on FPGA Platform

63%

Milik A. , Hrynkiewicz E.

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tom Vol, 58, No. 1

85-94

EN

The paper presents a set of algorithms dedicated for synthesis of reconfigurable logic controllers implemented on FPGA platform and programmed according to IEC1131 and EN61131. The program is compiled to hardware structure with a massive parallel processing. The developed method automatically allocates resources and operations. It controls resource usage and operation timing. Using mixed concept of operation allocation that considers operation timing and forms combinatorial chains of operations number of execution cycles can be reduced. An example of logic functions, PID controller and mixed arithmetic and logic programming examples are considered. Introducing the automatic implementation method allows flexible implementing the control algorithms. The maximal possible parallelism (limited only by the algorithm dependencies and available resources) is introduced.

4

An Efficient Hardware Implementation of Smith-Waterman Algorithm Based on the Incremental Approach

63%

Pułka A. , Milik A.

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tom Vol. 57, No. 4

489-496

EN

The paper presents optimized hardware structure applied to genome alignment search. The proposed methodology is based on dynamic programming. The authors show how starting from the original Smith-Waterman approach, the algorithm can be optimized and the evaluation process simplified and speeded-up. The main idea is based on the observations of growth trends in the adjacent cells of the systolic array, which leads to the incremental approach. Moreover various coding styles are discussed and the best technique allowing further reduction of resources is selected. The entire processing unit utilizes fully pipelined structure that is well balanced trade-off between performance and resource requirements. The proposed technique is implemented in modern FPGA structures and obtained results proved efficiency of the methodology comparing to other approaches in the field.

5

Dekompozycyjne metody syntezy przeznaczone dla układów CPLD

51%

Kania D. , Milik A. , Opara A.

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tom Vol. 49, nr 10

93-100

PL

W artykule przedstawiono dekompozycyjne metody syntezy opracowane dla struktur CPLD typu PAL. Prezentowane metody stanowią rozwinięcie klasycznej teorii dekompozycji Ashenhursta-Curtisa. Przedstawiono również zastosowanie binarnych diagramów decyzyjnych w procesie dekompozycji opracowanych dla układów CPLD typu PAL.

EN

This paper presents decomposition based logic synthesis methods for PAL-based CPLDs. Presented methods are based on classical Ashenhurst-Curtis decomposition theory. There is also presented application of Binary Decision Diagram in logic decomposition for PAL-based CPLDs.

6

On the systematic method of conditional control program execution by a PLC

51%

Milik A. , Chmiel M. , Hrynkiewicz E.

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tom Vol. 64, nr 1

161--170

EN

The paper presents an original idea of the selective control program execution that allows significant response time reduction. The exhaustive analysis of the PLC program performance is given. An analytic approach explains the idea of the selective control program evaluation and gives the requirements for its feasibility. There is presented a systematic and formal method of program analysis based on a data flow graph approach. The method generates acyclic graph from the control program that is subject of optimization, variable allocation and instruction generation. The graph approach allows determining variables dependencies and task partitioning required by selective program execution. The method utilize the hardware supported variable changes detection. It is transparent for system operation and enables evaluation of blocks that require update.