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2 International Journal of Microelectronics and Computer Science

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Inﬂuence of substrate meshing on the accuracy of EPFL substrate model for smart power ICs

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Stefanucci C. , Buccella P. , Kayal M. , Sallese J. M.

tom Vol. 5, nr 2

61--68

Minority carriers diffusion in Smart Power ICs substrate can be simulated in standard spice-like software using the EPFL Substrate Model. This model is based on a parasitic substrate network extracted from the integrated circuit layout following a given meshing strategy. In this work Design of Experiments (DOE) techniques are used to run a limited number of simulations to evaluate the inﬂuence of the meshing strategy on the accuracy of the model when compared to Technology Computer Aided Design (TCAD) simulations. A parasitic lateral BJT will be analyzed as two-dimensional case study with both spice-like and ﬁnite element simulations for the minority carriers diffusion. Using statistical analysis a linear model is developed to discover the main geometrical domains inﬂuencing the accuracy of the studied model.

Spice simulation of substrate potential shift in HVCMOS technologies

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Stefanucci C. , Buccella P. , Kayal M. , Sallese J.-M.

tom Vol. 6, nr 4

142--147

High voltage CMOS active devices inherently include a parasitic vertical PNP bipolar transistor. When activated it injects holes into the substrate causing a dangerous potential shift. In this work a spice-modeling approach based on transistor layout is presented to simulate substrate de-biasing in Smart Power ICs. The proposed model relies on a parasitic substrate network without the need of a parasitic BJT in HVCMOS compact models. The results are compared with TCAD simulations at different temperatures showing good agreement. Potential shift of the substrate is analysed for different geometrical configurations to estimate the effect of P+ grounding schemes and backside contact.