Wyniki wyszukiwania - Biblioteka Nauki

1

On-wafer wideband characterization: a powerful tool for improving the IC technologies

100%

Lederer D. , Raskin J. P.

Journal of Telecommunications and Information Technology

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2007

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tom nr 2

69-77

EN

In the present paper, the interest of wideband characterization for the development of integrated technologies is highlighted through several advanced devices, such as 120 nm partially depleted (PD) silicon-on-insulator (SOI) MOSFETs, 120 nm dynamic threshold (DT) voltage - SOI MOSFETs, 50 nm FinFETs as well as long-channel planar double gate (DG) MOSFETs.

2

Impact of Crosstalk into High Resistivity Silicon Substrate on the RF Performance of SOI MOSFET

80%

Ali K. B. , Neve C. R. , Gharsallah A. , Raskin J. P.

Journal of Telecommunications and Information Technology

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2010

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tom nr 4

93-100

EN

Crosstalk propagation through silicon substrate is a serious limiting factor on the performance of the RF devices and circuits. In this work, substrate crosstalk into high resistivity silicon substrate is experimentally analyzed and the impact on the RF behavior of silicon-on-insulator (SOI) MOS transistors is discussed. The injection of a 10 V peak-to-peak single tone noise signal at a frequency of 3 MHz ( fnoise) generates two sideband tones of ?56 dBm separated by fnoise from the RF output signal of a partially depleted SOI MOSFET at 1 GHz and 4.1 dBm. The efficiency of the introduction of a trap-rich polysilicon layer located underneath the buried oxide (BOX) of the high resistivity (HR) SOI wafer in the reduction of the sideband noise tones is demonstrated. An equivalent circuit to model and analyze the generation of these sideband noise tones is proposed.

3

Accurate SOI MOSFET characterization at microwave frequencies

80%

Raskin J. P. , Dambrine G. , Vanhoenacker D.

Electron Technology

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1999

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tom Vol. 32, No. 1/2

72-80

EN

The maturation of low cost SOI MOSFET technology in the microwave domain has brought about a need to develop specific characterization techniques. An original scheme is presented, which, by combining careful desigtn of probing and calibration structures, rigourous in situ calibration, and a new powerful direct extraction method, allows reliable identification of the parameters of the non-quasistatic small-signal model for MOSFET's. The extracted models is shown to be valid up to 40 GHz.

4

Deposition time and annealing effects on morphological and optical properties of ZnS thin films prepared by chemical bath deposition

80%

Chabou N. , Birouk B. , Aida M. S. , Raskin J. P.

Materials Science Poland

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2020

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tom Vol. 38, No. 4

508--517

EN

Nanocrystalline zinc sulfide (ZnS) thin films are prepared on glass substrates by chemical bath deposition (CBD) method using aqueous solutions of zinc chloride, thiourea ammonium hydroxide along with non-toxic complexing agent tri-sodium citrate in alkaline medium at 80 °C. The deposition time and annealing effects on the optical and morphological properties are studied. The morphological, compositional, and optical properties of the films are investigated by scanning electron microscopy (SEM), X-ray energy dispersive spectroscopy (EDAX) and UV-Vis spectroscopy. SEM micrographs exhibit uniform surface coverage. UV-Vis (300 nm to 800 nm) spectrophotometric measurements show transparency of the films (transmittance ranging from 69 % to 81 %), with a direct allowed energy band gap in the range of 3.87 eV to 4.03 eV. After thermal annealing at 500 °C for 120 min, the transmittance increases up to 87 %.

5

Direct extraction techniques of microwave small-signal model and technological parameters for sub-quarter micron SOI MOSFETs

80%

Goffioul M. , Vanhoenacker D. , Raskin J. P.

Journal of Telecommunications and Information Technology

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2000

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tom nr 3-4

59-66

EN

Original extraction techniques of microwave small-signal model and technological parameters for SOI MOSFETs are presented. The characterization method combines careful design of probing and calibration structures, rigorous in situ calibration and a powerful direct extraction method. The proposed characterization procedure is directly based on the physical meaning of each small-signal behavior of each model parameter versus bias conditions, the high frequency equivalent circuit can be simplified for extraction purposes. Biasing MOSFETs under depletion, strong inversion and saturation conditions, certain technological parameters and microwave small-signal elements can be extracted directly from the measured S-parameters. These new extraction techniques allow us to understand deeply the behavior of the sub-quarter micron SOI MOSFETs in microwave domain and to control their fabrication process.

6

Comparison of microwave performances for sub-quarter micron fully- and partially-depleted SOI MOSFETs

80%

Goffioul M. , Dambrine G. , Vanhoenacker D. , Raskin J. P.

Journal of Telecommunications and Information Technology

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2000

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tom nr 3-4

72-80

EN

The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lenghts and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 žm FD SOI n-MOSFETs with a total gate width of 100 žm present a state-of-the-art minimum noise figure of 0.8 dB and high associated gain of 13 dB at 6 GHz for V(ds) = 0.75 V and P(dc) < 3 mW. A maximum extrapolated oscillation frequency of about 70 GHz has been obtained at V(ds) = 1 V and J(ds) = 100 mA/mm. This new generation of MOSFETs presents very good analogical and digital high speed performances with a low power consumption which make them extremely attractive for high frequency portable applications such as the wireless communications.

7

Deposition time and annealing effects on morphological and optical properties of ZnS thin films prepared by chemical bath deposition

80%

Chabou N. , Birouk B. , Aida M. S. , Raskin J. P.

Materials Science Poland

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2019

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tom Vol. 37, No. 3

404--416

EN

Nanocrystalline zinc sulfide thin films were prepared on glass substrates by chemical bath deposition method using aqueous solutions of zinc chloride, thiourea ammonium hydroxide along with non-toxic complexing agent trisodium citrate in alkaline medium at 80 °C. The effect of deposition time and annealing on the properties of ZnS thin films was investigated by X-ray diffraction, scanning electron microscopy, optical transmittance spectroscopy and four-point probe method. The X-ray diffraction analysis showed that the samples exhibited cubic sphalerite structure with preferential orientation along 〈2 0 0〉 direction. Scanning electron microscopy micrographs revealed uniform surface coverage, UV-Vis (300 nm to 800 nm) spectrophotometric measurements showed transparency of the films (transmittance ranging from 69 % to 81 %), with a direct allowed energy band gap in the range of 3.87 eV to 4.03 eV. After thermal annealing at 500 °C for 120 min, the transmittance increased up to 87 %. Moreover, the electrical conductivity of the deposited films increased with increasing of the deposition time from 0.35 × 10−4 Ω·cm−1 to 2.7 × 10−4 Ω·cm−1.

8

Charge-pumping characterization of SOI devices fabricated by means of wafer bonding over pre-patterned cavities

61%

Głuszko G. , Łukasiak L. , Kilchytska V. , Chung T. M. , Olbrechts B. , Flandrie D. , Raskin J. P.

Journal of Telecommunications and Information Technology

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2007

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tom nr 3

61-66

EN

The quality of the silicon-buried oxide bonded interface of SOI devices created by thin Si film transfer and bonding over pre-patterned cavities, aiming at fabrication of DG and SON MOSFETs, is studied by means of chargepumping (CP) measurements. It is demonstrated that thanks to the chemical activation step, the quality of the bonded interface is remarkably good. Good agreement between values of front-interface threshold voltage determined from CP and I-V measurements is obtained.

9

High frequency four noise parameters of silicon-on-insulator-based technology MOSFET : prospects for application to low noise RF intergrated circuits

61%

Dambrine G. , Raskin J. P. , Picheta L. , Vanhoenacker D. , Colinge J. P. , Cappy A.

Electron Technology

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1999

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tom Vol. 32, No. 1/2

81-87

EN

An exhaustive experimental study of the high frequency noise properties of MOSFET in Silicon-on-Insulator (SOI) technology is presented. Various gate geometries are fabricated to study the influence of effective channel length and gate finger width on the four noise parameters. The high level of MOSFET sensitivity to the minimum noise matching conditions is demonstrated. From experimental results, optimization ways to realize ultra low noise amplifiers are discussed. The capability of the fully depleted standard SOI CMOS process for realizing low noise amplifiers for multigigahertz portable communication systems is shown. A minimum noise figure of about 0.7 dB and an available gain of 15 dB at 2 GHz have been obtained in the case of 0.6 µm effective gate length processes for applications in upper frequency range.