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1
Content available The Effect of High Temperature Annealing on Fluorine Distribution Profile and Electro-Physical Properties of Thin Gate Oxide Fluorinated by Silicon Dioxide RIE in CF4 Plasma
100%
Kalisz M. , Głuszko G. , Beck R. B.
Journal of Telecommunications and Information Technology
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2010
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tom nr 1
25-28
EN
This study describes the effects of high temperature annealing performed on structures fluorinated during initial silicon dioxide reactive ion etching (RIE) process in CF4 plasma prior to the plasma enhanced chemical vapour deposition (PECVD) of the final oxide. The obtained results show that fluorine incorporated at the PECVD oxide/Si interface during RIE is very stable even at high temperatures. Application of fluorination and high temperature annealing during oxide layer fabrication significantly improved the properties of the interface (Ditmb decreased), as well as those of the bulk of the oxide layer (Qeff decreased). The integrity of the oxide (higher Vbd ) and its uniformity (Vbd distribution) are also improved.
2
Content available Novel Method of Improving Electrical Properties of Thin PECVD Oxide Films by Fluorination of Silicon Surface Region by RIE in RF CF4 Plasma
100%
Kalisz M. , Głuszko G. , Beck R. B.
Journal of Telecommunications and Information Technology
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2010
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tom nr 1
20-24
EN
This study describes a novel technique to form good quality low temperature oxide (< 350 C degree). Low temperature oxide was formed by N2O + SiH4:N2 plasma in a plasma enhanced chemical vapour deposition (PECVD) system on the silicon surface reactively etched in CF4 plasma (RIE - reactive ion etching). The fabricated oxide demonstrated excellent (for low temperature dielectric formation process) currentvoltage (I-V) characteristics, such as: low leakage current, high breakdown voltage and good reliability. Experimental results indicate that the proposed method of fluorine incorporation into the SiO2/Si inteface improves electrical parameters of MOS structures.
3
Charakteryzacja struktur SOI za pomocą 3-poziomowej metody pompowania ładunku
100%
Głuszko G. , Łukasiak L. , Jakubowski A.
Elektronika : konstrukcje, technologie, zastosowania
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2008
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tom Vol. 49, nr 1
72-74
PL
Przedstawiono próbę wyznaczenia energetycznego rozkładu gęstości pułapek powierzchniowych na górnej powierzchni granicznej dielektryk-półprzewodnik struktur SOI (diod PIN z bramką oraz tranzystorów MOS) za pomocą trójpoziomowej metody pompowania ładunku. Otrzymane wyniki zweryfikowano poprzez porównanie z rezultatami charakteryzacji dwupoziomową metodą pompowania ładunku.
EN
This paper presents for the first time the results of 3-level chargepumping measurements of SOI structures. Transistors with body contact as well as PIN gated diodes are used in measurements. The aim of these measurements is to provide information on the energy distribution of interface traps at the front Si-SiO2 interface.
4
Content available Charge-pumping characterization of FILOX vertical MOSFETs
100%
Głuszko G. , Łukasiak L. , Ashburn P.
Journal of Telecommunications and Information Technology
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2007
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tom nr 3
73-77
EN
This paper presents for the first time the results of charge-pumping (CP) measurements of FILOX vertical transistors. The aim of these measurements is to provide information on the density of interface traps at the Si-SiO2 interface fabricated in a non-standard process. Flat-band and threshold voltage, as well as density of interface traps are determined. Good agreement between threshold-voltage values obtained from CP and I-V measurements is observed.
5
Content available Characterization of SOI MOSFETs by means of charge-pumping
88%
Głuszko G. , Szostak S. , Gottlob H. , Lemme M. , Łukasiak L.
Journal of Telecommunications and Information Technology
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2007
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tom nr 3
67-72
EN
This paper presents the results of charge-pumping measurements of SOI MOSFETs. The aim of these measurements is to provide information on the density of interface traps at the front and back Si-SiO2 interface. Three-level charge-pumping is used to obtain energy distribution of interface traps at front-interface.
6
Content available Charge-pumping characterization of SOI devices fabricated by means of wafer bonding over pre-patterned cavities
75%
Głuszko G. , Łukasiak L. , Kilchytska V. , Chung T. M. , Olbrechts B. , Flandrie D. , Raskin J. P.
Journal of Telecommunications and Information Technology
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2007
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tom nr 3
61-66
EN
The quality of the silicon-buried oxide bonded interface of SOI devices created by thin Si film transfer and bonding over pre-patterned cavities, aiming at fabrication of DG and SON MOSFETs, is studied by means of chargepumping (CP) measurements. It is demonstrated that thanks to the chemical activation step, the quality of the bonded interface is remarkably good. Good agreement between values of front-interface threshold voltage determined from CP and I-V measurements is obtained.
7
Content available Applying shallow nitrogen implantation from rf plasma for dual gate oxide technology
75%
Bieniek T. , Beck R. B. , Jakubowski A. , Głuszko G. , Konarski P. , Ćwil M.
Journal of Telecommunications and Information Technology
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2007
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tom nr 3
3-8
EN
The goal of this work was to study nitrogen implantation from plasma with the aim of applying it in dual gate oxide technology and to examine the influence of the rf power of plasma and that of oxidation type. The obtained structures were examined by means of ellipsometry, SIMS and electrical characterization methods.
8
Modelowanie prądu pompowania ładunku w dwubramkowych strukturach MOS z bardzo cienką warstwą aktywną
75%
Łukasiak L. , Tomaszewski D. , Sawicka A. , Głuszko G. , Iwanowicz M. , Jakubowski A.
Elektronika : konstrukcje, technologie, zastosowania
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2008
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tom Vol. 49, nr 9
92-95
PL
W pracy przeanalizowano wpływ grubości warstwy aktywnej oraz tlenku bramkowego na prąd pompowania ładunku w dwubramkowych strukturach MOS z bardzo cienką warstwą aktywną. Sprawdzono także, czy istnieje możliwość oddzielnego badania każdej powierzchni granicznej za pomocą metody pompowania ładunku.
EN
The influence of body and gate-oxide thickness on charge pumping current in double-gate MOS structures is analyzed to find out whether it is possible to perform charge-pumping studies of each interface separately.
9
Content available remote Charge pumping characterization of MISFETs with SiO2/BaTiO3 as a gate stack
75%
Firek P. , Głuszko G. , Łukasiak L. , Szmidt J. , Jakubowski A. , Sochacki M.
Przegląd Elektrotechniczny
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2014
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tom R. 90, nr 9
26-28
EN
The results of charge pumping measurements of MISFETs with SiO2/BaTiO3 as a gate stack were presented and discussed. The characterization method was used for verification of thershold voltage and trap density values obtained by static current-voltage (I-V) measurements.
PL
W pracy zaprezentowano i przeanalizowano wyniki pomiarów tranzystorów MISFET wykorzystujących dwuwarstwowy dielektryk SiO2/BaTiO3. Pomiary wykonano przy użyciu metody pompowania ładunku. Stosowana metoda charakteryzacji posłużyła do weryfikacji wartości napięcia progowego tranzystora oraz gęstości pułapek powierzchniowych uzyskanych w oparciu o pomiar statycznych charakterystyk prądowonapięciowych (I-V) tranzystora.
10
Content available The influence of annealing (900?C) of ultra-thin PECVD silicon oxynitride layers
63%
Mroczyński R. , Głuszko G. , Beck R. B. , Jakubowski A. , Ćwil M. , Konarski P. , Hoffman P. , Schmeißer D.
Journal of Telecommunications and Information Technology
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2007
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tom nr 3
16-19
EN
This work reports on changes in the properties of ultra-thin PECVD silicon oxynitride layers after high- temperature treatment. Possible changes in the structure, composition and electrophysical properties were investigated by means of spectroscopic ellipsometry, XPS, SIMS and electrical characterization methods (C-V, I-V and charge- pumping). The XPS measurements show that SiOxNy is the dominant phase in the ultra-thin layer and high-temperature annealing results in further increase of the oxynitride phase up to 70% of the whole layer. Despite comparable thickness, SIMS measurement indicates a densification of the annealed layer, because sputtering time is increased. It suggests complex changes of physical and chemical properties of the investigated layers taking place during high-temperature annealing. The C-V curves of annealed layers exhibit less frequency dispersion, their leakage and charge-pumping currents are lower when compared to those of as-deposited layers, proving improvement in the gate structure trapping properties due to the annealing process.
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