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1 Electronics and Telecommunications Quarterly

1 2008

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Hardware architecture of a parallel system for lane detection

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Pankiewicz P. , Powiertowski W. , Roszak G.

2008

tom Vol. 54, No 4

547-560

The aim of this paper is to describe in detail the hardware implementation of the lane detection algorithm presented at 15th International Conference "Mixed Design of Integrated Circuits and Systems". During introductory research several approaches to edge and line detection were analyzed, which resulted in optimal combination for future hardware implementation. The proposed algorithm is based on the Canny edge detector and the linear Hough transform for line detection. The system was pre-developed using the Matlab environment. The next step was the synthesizable hardware description using VHDL. A wide range of testing procedures for structural and behavioral verification was designed. The presented evaluation of both hardware and software simulation, and synthesis results suggested high capabilities of designed architecture, which have been proven during real-time hardware tests of the system.