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2 International Journal of Microelectronics and Computer Science

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Spice simulation of substrate potential shift in HVCMOS technologies

100%

Stefanucci C. , Buccella P. , Kayal M. , Sallese J.-M.

tom Vol. 6, nr 4

142--147

High voltage CMOS active devices inherently include a parasitic vertical PNP bipolar transistor. When activated it injects holes into the substrate causing a dangerous potential shift. In this work a spice-modeling approach based on transistor layout is presented to simulate substrate de-biasing in Smart Power ICs. The proposed model relies on a parasitic substrate network without the need of a parasitic BJT in HVCMOS compact models. The results are compared with TCAD simulations at different temperatures showing good agreement. Potential shift of the substrate is analysed for different geometrical configurations to estimate the effect of P+ grounding schemes and backside contact.

Measurement and performance evaluation of a silicon on insulator pixel matrix

88%

Ntavelis D. , Harik L. , Sallese J.-M. , Kayal M. , Hatzopoulos A.

tom Vol. 1, nr 3

299-304

A new technique for driving silicon-on-insulator pixel matrixes has been proposed in |1|, which was based on transient charge pumping for evacuating the extra photo-generated charges from the body of the transistor. An 8x8 pixel matrix was designed and fabricated using the above technique. In this paper, the measurement set-up is described and the performance evaluation procedure is given, together with results of its implementation on the fabricated pixel matrix. The results show the applicability of the charge pumping technique and the effective operation of the image sensor.