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1 International Journal of Electronics and Telecommunications

1 2023

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Solving the Problem of Discrete Process Control Synthesis Using Optimization on a Sliding Interval

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Julayeva Z. , Wójcik W. , Kashaganova G. , Togzhanova K. , Mambetov S.

tom Vol. 69, No. 2

383--389

The paper brings forward an idea of multi-threaded computation synchronization based on the shared semaphored cache in the multi-core CPUs. It is dedicated to the implementation of multi-core PLC control, embedded solution or parallel computation of models described using hardware description languages. The shared semaphored cache is implemented as guarded memory cells within a dedicated section of the cache memory that is shared by multiple cores. This enables the cores to speed up the data exchange and seamlessly synchronize the computation. The idea has been verified by creating a multi-core system model using Verilog HDL. The simulation of task synchronization methods allows for proving the benefits of shared semaphored memory cells over standard synchronization methods. The proposed idea enhances the computation in the algorithms that consist of relatively short tasks that can be processed in parallel and requires fast synchronization mechanisms to avoid data race conditions.