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EN
This paper presents a simple circuit technique to reduce gain variability with PVT variations in cascode amplifiers using a body-biasing scheme, while enhancing the overall gain of the amplifier. Simulation results of a standard telescopic-cascode amplifier, in two different nanoscale CMOS technologies (130 nm and 65 nm) show that the proposed compensated circuit amplifier exhibits a (DC) gain variability smaller (below ± 0.5 dB) than the original (uncompensated) circuit, while reaching a gain enhancement of about 3 dB. The required auxiliary biasing circuit dissipates around 5% of the main amplifier circuit.
EN
A low-voltage RF CMOS receiver front-end and an energy harvesting power circuit for a piezoelectric source are presented as a co-designed solution for a Wireless Sensor Node. A MOSFET-only Wideband balun LNA with noise cancelling and a 0.6 V supply voltage is designed in conjunction with a passive mixer. The passive mixer operates in current mode, allowing a minimal introduction of voltage noise and a good linearity. The receiver front-end reaches a total voltage conversion gain of 31 dB, a 0.1-5.2 GHZ bandwidth, an IIP3 value of -1.35 dBm, and a noise figure inferior to 9 dB. The total power consumption is 1.95 mW. The energy harvesting power circuit consists of an active full bridge cross-coupled rectifier followed by a low-dropout (LDO) regulator, and it is able to guarantee a power output of 6 mW with a regulated output voltage of 0.6 V, for typical vibration patterns.
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EN
In this paper we present a MOSFET-only implementation of a balun LNA. This LNA is based on the combination of a common-gate and a common-source stage with cancellation of the noise of the common-gate stage. In this circuit, we replace resistors by transistors, to reduce area and cost, and to minimize the effect of process and supply variations and mismatches. In addition, we obtain a higher gain for the same voltage drop. Thus, the LNA gain is optimized and the noise figure (NF) is reduced. We derive equations for the gain, input matching and NF. The performance of this new topology is compared with that of a conventional LNA with resistors. Simulation results with a 130 nm CMOS technology show that we obtain a balun LNA with a peak gain of 20.2 dB (about 2 dB improvement), and a spot NF lower than 2.4 dB. The total power consumption is only 4.8 mW for a bandwidth higher than 6 GHz.
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Content available Analysis and design of CMOS coupled multivibrators
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EN
In this paper a wideband MOS quadrature oscillator constituted by two multivibrators is presented. Two different forms of coupling, named here as soft and hard, are investigated. Simulations are performed in a 0.13 žm CMOS technology to obtain the tuning range, the synchronization transients, and the influence of mismatches in timing capacitors and charging currents on synchronization. It is found that hard coupling reduces the quadrature error (about 1°, with 5% mismatches in timing capacitors and charging currents) and results in a low phase-noise (about 2 dB improvement) with respect to soft coupling. Either a single multivibrator or coupled multivibrators can be locked to an external synchronizing harmonic frequency, and the locking range is investigated by simulations. The simulations are done for oscillators covering the WTMS frequency bands.
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Content available remote Wide Tuning Range Quadrature VCO Using Coupled Multivibrators
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EN
Two emitter-coupled multivibrators are coupled to produce a quadrature current-/voltage controlled oscillator with wide frequency tuning range (which can be wider than one decade). The tuning range, the achievable frequency of oscillation, and the synchronization transients are investigated by simulation. The influence of mismatches of timing capacitors and charging currents on synchronization is also investigated. The results of simulations for different couplings show that one can find a design with low quadrature error, low phase noise and wide tuning range. This confirms the potential of the proposed VCO for RJF applications.
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Content available remote Regulated common-gate TIA with noise improvement for radiation detectors
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EN
A Transimpedance Amplifier (TIA) is a device which performs current-voltage conversion and signal shaping. The most commonly used solution is an Avalanche Photo-Diode (APD) as radiation detector with a feedback TIA. Recently, Silicon Photo-Multipliers (SiPMs), have proven to be good alternatives. The main objective in this paper is to show, evaluate and compare the behavior of a regulated common-gate (RCG) TIA when the light sensitive device is an APD or a SiPM. We will also present two alternative circuits based on the RCG topology. The first can be resumed to the insertion of a transistor, responsible for an improvement in the output noise response of the TIA. This solution proves itself to be a good alternative, since it will improve the Signal-to-Noise Ratio (SNR) of the circuit by around 3 dB, with negligible penalty in consumption (only 2%). The second alternative will be a proposed differential version of the RCG topology, in which the first solution will be included. These two latter solutions will only be tested with a SiPM at the input. We will also study the RCG topology in a RF front-end, providing there is a passive mixer at the TIA’s input. The proposed circuits are simulated with standard CMOS technology (UMC 130 nm), from a 1.2 V supply.
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EN
We present a balun LNA with noise and distortion cancellation using double feedforward. A common-gate and a common-source stage are combined, and their resistive loads are replaced by transistors biased close to saturation to allows low supply voltage, without gain degradation. The proposed feedforward boosts the LNA gain and reduces the noise figure (NF). Simulation results with a 130 nm CMOS technology show that the gain is up to 24 dB and the NF is below 3.2 dB. The total power dissipation is 2.25 mW, leading to an FoM of 6.4 mW-1 with 0.6 V supply.
EN
In this paper we present a MOSFET-only implementation of a wideband Gilbert Cell. The circuit uses a commongate topology for a wideband input match, capable to cover the Wireless Medical Telemetry Service (WMTS) frequency bands of 600 MHz and 1.4 GHz. In this circuit the load resistors are replaced by transistors in triode region, to reduce area and cost, and minimize the effects of process and supply variations and mismatches. In addition, we obtain a higher gain for the same DC voltage drop, with a reduced impact on the noise figure (NF). The performance of this topology is compared with that of a conventional mixer with load resistors. Simulation results show that a peak gain of 20.6 dB (about 6 dB improvement) and a NF about of 11 dB for the 600 MHz band. The total power consumption is 3.6 mW from a 1.2 V supply.
EN
This paper presents our research and development work on new circuits and topologies based on Magnetic RAM for use as configuration memory elements of reconfigurable arrays. MRAM provides non volatility with cell areas and with access speeds comparable to those of SRAM and with lower process complexity than FLASH memories. The new memory cells take advantage of the Thermal Assisted Switching (TAS) writing technique to solve the drawbacks of the more common Field Induced Magnetic Switching writing technique. The CMOS circuit structures to implement the main components for reading and writing the MTJ cells have been developed, characterized and evaluated. A scaled down prototype of a coarse grain reconfigurable array that employs the TAS-MRAM elements as configuration memory has been designed and electrically simulated pre- and post- layout. The results obtained for all the circuit elements, namely the storage cells and the current generators, indicate that the new configuration memory cells can provide a very promising technological solution for run-time reconfigurable hardware devices. The prototype has been manufactured using a standard process 0.35μm 4-Metal CMOS process technology and should be under test in the foreseeable future.
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