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EN
Companding, as a variant of audio level compression, can help reduce the dynamic range of an audio signal. In analog (digital) systems, this can increase the signal-to-noise ratio (signal to quantization noise ratio) achieved during transmission. The µ-law algorithm that is primarily used in the digital telecommunication systems of North America and Japan, adapts a companding scheme that can expand small signals and compress large signals especially at the presence of high peak signals. In this paper, we present a novel multi-exponential companding function that can achieve more uniform compression on both large and small signals so that the relative signal strength over the time is preserved. That is, although larger signals may get considerably compressed, unlike µ-law algorithm, it is guaranteed that these signals after companding will definitely not be smaller than expanded signals that were originally small. Performance of the proposed algorithm is compared with µ-law using real audio signal, and results show that the proposed companding algorithm can achieve much smaller quantization errors with a modest increase in computation time.
EN
High Performance Computing (HPC) architectures are being developed continually with an aim of achieving exascale capability by 2020. Processors that are being developed and used as nodes in HPC systems are Chip Multiprocessors (CMPs) with a number of cores. In this paper, we continue our effort towards a better processor allocation process. The Processor Allocator (PA) and Job Scheduler (JS) proposed and implemented in our previous works are explored in the context of its best location on the chip. We propose a system, where all locations on a chip can be analyzed, considering energy used by Network-on-Chip (NoC), PA and JS, and processing elements. We present energy models for the researched CMP components, mathematical model of the system, and experimentation system. Based on experimental results, proper placement of PA and JS on a chip can provide up to 45% NoC energy savings.
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Content available remote Energy characteristic of a processor allocator and a network-on-chip
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EN
Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.
EN
In this paper, analytical expressions for the distribution of the envelope and phase of linearly modulated signals such as BPSK, M-PSK, and M-QAM in AWGN are presented. We perform numerical simulations for different orders of signal constellations. The results show that the proposed theoretical models are in excellent agreement with the estimated distributions from various numerical experiments.
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