Warianty tytułu
Języki publikacji
Abstrakty
This paper deals with a hardware implementation of an RSA cryptosystem. A behavioural and RT-level model of the RSA cryptosystem was created. The authors focus particularly on the behavioural model. The behavioural model is fully parameterized and was synthesized for keys of two lengths and several clock speeds. The paper encloses sunthesis results regarding area and performance in meaning of time needed to pass the whole computation cycle. Basing on them a comparison is carried out for behavioural and RT-level implementation.
Słowa kluczowe
Czasopismo
Rocznik
Tom
Strony
600-605
Opis fizyczny
Bibliogr. 9 poz.
Twórcy
autor
autor
autor
autor
- Institute of Electron Technology, al. Lotników 32/46, 02-668 Warszawa, Poland
Bibliografia
Typ dokumentu
Bibliografia
Identyfikatory
Identyfikator YADDA
bwmeta1.element.baztech-article-BWA1-0001-1054