Warianty tytułu
Przetwornik logarytmujący o dużej dokładności
Języki publikacji
Abstrakty
A novel BiCMOS voltage-to-voltage converter with logarithmic characteristics and very high accuracy is presented. The relationship between the emitter current and the base-emitter voltage in bipolar transistors is used to realize the logarithmic function. With 1.8 supply voltage, the total power consumption is less than 15.75 mW and a Log error of <-36dB is shown in the ADS simulations. Compared to the other method in the literature, very better accuracy in logarithm calculation is achieved. The proposed method can be used in arithmetical operation circuits like analog processors.
Przedstawiono nowy przetwornik logarytmujący w technologii BiCMOS. Do realizacji funkcji logarytmującej użyto zależności między prądem emitera i napięciem baza-emiter w tranzystorze bipolarnym. Przy napięciu zasilającym 1.8V pobór mocy był mniejszy niż 15.75 mWa błąd logarytmowania byt mniejszy niż -36dB. W porównaniu z podobnymi układami prezentowanymi w literaturze osiągnięto lepszą dokładność.
Czasopismo
Rocznik
Tom
Strony
150-153
Opis fizyczny
Bibliogr. 12 poz., rys., tab.
Twórcy
autor
autor
autor
- Electrical Department, Iran University of Science and Technology, Tehran, Iran, aghanaatianee.iust.ac.ir
Bibliografia
- [1] Chris D. Holdenried, James W. Haslett, John G. McRory, R. Douglas Beards, and A. J. BergsmaJ. A DC-4-GHz True Logarithmic Amplifier: Theory and Implementation, IEEE Journal of Solid-State Circuits, Vol. 37, No. 10, October2002.
- [2] Sanchi Harnsoongnoen, Chiranut Sa-ngiamsak, Poonsak Intarakul and Rardchawadee Silapunt, "Logarithmic and Antilogarithmic Circuit with Gate-to-Substrate Biasing Technique", ITC-CSCC, 2008.
- [3] R. F. Wolffenbuttel, Digitally Programmable Accurate Current Source for Logarithmic Control of The Amplification or Attenuation in again Cell, IEEE Journal of Solid-State Circuit, Vol. 23, pp. 767-773, 1988.
- [4] A. B. Grebene, Bipolar and MOS integrated Circuit Design,John Wiley & Sons, New York, 1984.
- [5] B. Gilbert, "Synchronous logarithmic amplifier," U.S. Patent 5 298 811, Mar. 29, 1994.
- [6] A. Garskamp, "Logarithmic amplifier with sequentially limiting amplifier stages," U.S. Patent 5 049 829, Sept. 17, 1991.
- [7] K. Kimura, "Logarithmic amplifying.circuit based on the biasoffset technique," U.S. Patent 5 506 537, Apr. 9, 1996.
- [8] F. W. Olsen and E. J. Tasillo, "Psuedo logarithmic step adder," U.S. Patent 5 221 907, June 22, 1993.
- [9] Quoc-hoang duong, T.kien nguyen and Sang-gug lee, CMOS Exponential Current-to-Voltage Circuit Based on Newly Proposed Approximation Method, ISCAS, 2004.
- [10] Carlos A. De La Cruz-Blas and Antonio Lopez-Martin, Compact Power-Efficient CMOS Exponential Voltage-to-Voltage Converter, ISCAS 2006.
- [11] F. Bergouignan, N. Abouchi, R. Grisel, G. Caille, J. Caranana, Designs Of A Logarithmic and Exponential Amplifiers Using Current Conveyors, ICECS 1996.
- [12] Wci hsing Liii, Clieng-Chicli Clieilg and Shcn-I tian TA, Realisation of exponential V-I converter using composite NMOS transistors, Electronics Letters 6th January 2000 Val. 36 No. I.
Typ dokumentu
Bibliografia
Identyfikatory
Identyfikator YADDA
bwmeta1.element.baztech-article-BPS1-0044-0079