Czasopismo
Tytuł artykułu
Autorzy
Wybrane pełne teksty z tego czasopisma
Warianty tytułu
Konferencja
Federated Conference on Computer Science and Information Systems (16 ; 02-05.09.2021 ; online)
Języki publikacji
Abstrakty
Modern safety-critical embedded systems have to be time-deterministic to guarantee safety. One source of time-nondeterminism are interrupts. This paper shows how to mitigate their influence in the system on a commercially available processor IP (Codasip uRISC) can be modified to exhibit time-determinism in real-time workloads and isolate interrupts. We extend the processor with fine-grained multithreading and isolated interrupt handling to localize time-nondeterminism caused by interrupts. We show a comparison between original and extended processors on a selection of TACleBench benchmarks. For interrupt-driven workloads, ideal interrupt isolation is achieved. The proposed modification can be used on other in-order single-issue processors.
Rocznik
Tom
Strony
495--500
Opis fizyczny
Bibliogr. 17 poz., tab., wykr., rys.
Twórcy
autor
- Faculty of Electrical Engineering, Czech Technical University in Prague, kostama7@fel.cvut.cz
autor
- Czech Institute of Informatics, Robotics and Cybernetics, Czech Technical University in Prague, michal.sojka@cvut.cz
Bibliografia
- 1. T. Mitra, “INVITED time-predictable computing by design: Looking back, looking forward,” in 2019 56th ACM/IEEE Design Automation Conference (DAC), pp. 1-4, ISSN: 0738-100X.
- 2. H. Ding, Y. Liang, and T. Mitra, “WCET-centric partial instruction cache locking,” in DAC Design Automation Conference 2012, pp. 412-420, ISSN: 0738-100X.
- 3. D. Sanchez and C. Kozyrakis, “Vantage: scalable and efficient fine-grain cache partitioning,” ACM SIGARCH Computer Architecture News, vol. 39, no. 3, pp. 57-68. http://dx.doi.org/10.1145/2024723.2000073
- 4. G. Gracioli, R. Tabish, R. Mancuso, R. Mirosanlou, R. Pellizzoni, and M. Caccamo, “Designing mixed criticality applications on modern heterogeneous MPSoC platforms,” in 31st Euromicro Conference on Real-Time Systems (ECRTS 2019), ser. Leibniz International Proceedings in Informatics (LIPIcs), S. Quinton, Ed., vol. 133. Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik. http://dx.doi.org/10.4230/LIPIcs.ECRTS.2019.27. ISBN 978-3-95977-110-8 pp. 27:1-27:25, ISSN: 1868-8969.
- 5. M. Schoeberl, B. Rouxel, and I. Puaut, “A time-predictable branch predictor,” in Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, ser. SAC ’19. Association for Computing Machinery. http://dx.doi.org/10.1145/3297280.3297337. ISBN 978-1-4503-5933-7 pp. 607-616.
- 6. S. A. Edwards and E. A. Lee, “The case for the precision timed (PRET) machine,” in Proceedings of the 44th annual Design Automation Conference, ser. DAC ’07. Association for Computing Machinery. http://dx.doi.org/10.1145/1278480.1278545. ISBN 978-1-59593-627-1 pp. 264-265.
- 7. M. Zimmer, D. Broman, C. Shaver, and E. A. Lee, “FlexPRET: A processor platform for mixed-criticality systems,” in 2014 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS). http://dx.doi.org/10.1109/RTAS.2014.6925994 pp. 101-110, ISSN: 1545-3421.
- 8. M. Schoeberl, P. Schleuniger, W. Puffitsch, F. Brandner, C. W. Probst, S. Karlsson, and T. Thorn, “Towards a time-predictable dual-issue microprocessor: The patmos approach,” vol. 18. http://dx.doi.org/10.4230/OA-SIcs.PPES.2011.11 p. 11.
- 9. C. Sung, M. Kusano, and C. Wang, “Modular verification of interrupt-driven software,” in 2017 32nd IEEE/ACM International Conference on Automated Software Engineering (ASE). http://dx.doi.org/10.1109/ASE.2017.8115634 pp. 206-216.
- 10. Y. Wang, L. Wang, T. Yu, J. Zhao, and X. Li, “Automatic detection and validation of race conditions in interrupt-driven embedded software,” in Proceedings of the 26th ACM SIGSOFT International Symposium on Software Testing and Analysis, ser. ISSTA 2017. Association for Computing Machinery. http://dx.doi.org/10.1145/3092703.3092724. ISBN 978-1-4503-5076-1 pp. 113-124.
- 11. M. Pan, S. Chen, Y. Pei, T. Zhang, and X. Li, “Easy modelling and verification of unpredictable and preemptive interrupt-driven systems,” in 2019 IEEE/ACM 41st International Conference on Software Engineering (ICSE). http://dx.doi.org/10.1109/ICSE.2019.00037 pp. 212-222, ISSN: 1558-1225.
- 12. E. Lee, J. Reineke, and M. Zimmer, “Abstract PRET machines,” in 2017 IEEE Real-Time Systems Symposium (RTSS). http://dx.doi.org/10.1109/RTSS.2017.00041 pp. 1-11, ISSN: 2576-3172.
- 13. Z. Prikryl, “Fast simulation of pipeline in ASIP simulators,” in 2014 15th International Microprocessor Test and Verification Workshop. http://dx.doi.org/10.1109/MTV.2014.18 pp. 10-15, ISSN: 2332-5674.
- 14. P. Sláma, “Instruction level parallelism in modern processors,” Master Thesis, BUT, 2020.
- 15. M. Fajčík, “Automation of verification using artificial neural networks,” Master Thesis, BUT, 2016.
- 16. M. Fajcik, P. Smrz, and M. Zachariasova, “Automation of processor verification using recurrent neural networks,” in 2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV). http://dx.doi.org/10.1109/MTV.2017.15 pp. 15-20, ISSN: 2332-5674.
- 17. H. Falk, S. Altmeyer, P. Hellinckx, B. Lisper, W. Puffitsch, C. Rochange, M. Schoeberl, R. B. Sørensen, P. Wägemann, and S. Wegener, “TACLeBench: A benchmark collection to support worst-case execution time research,” in 16th International Workshop on Worst-Case Execution Time Analysis. http://dx.doi.org/10.4230/OASIcs.WCET.2016.2
Uwagi
1. Track 3: Software, System and Service Engineering
2. Session: Joint 41st IEEE Software Engineering Workshop and 8th International Workshop on Cyber-Physical Systems
Typ dokumentu
Bibliografia
Identyfikatory
Identyfikator YADDA
bwmeta1.element.baztech-af9bfa06-47a6-4cf6-b491-5dfba3a4ae63