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Realization of logic integrated circuits in VeSTIC process - design, fabrication, and characterization

Domański Krzysztof, Głuszko Grzegorz, Sierakowski Andrzej, Tomaszewski Daniel, Szmigiel Dariusz

International Journal of Microelectronics and Computer Science

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2018

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Vol. 9, nr 3

123--132

EN

A design and manufacturing of test structures for characterization of logic integrated circuits in a VeSTIC process developed in ITE, are described. Two variants of the VeSTIC processs have been described. A role and sources of the process variability have been discussed. The VeSFET I-V characteristics, the logic cell static characteristics, and waveforms of the 53-stage ring oscillator are presented. Basic parameters of the VeSFETs have been determined. The role of the process variability and of the parasitic elements introduced by the conservative circuit design, e.g. wide conductive lines connecting the devices in the circuits, have been discussed. Based on the inverter layout and on the process specification, the parasitic elements of the inverter equivalent circuit have been extracted. The inverter propagation times, the ring oscillator frequency, and their dependence on the supply bias have been determined.

2

Synthesis of finite state machines for implementation with programmable structures

Łuba T., Borowik G., Kraśniewski A.

Electronics and Telecommunications Quarterly

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2009

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Vol. 55, No 2

183-200

EN

Sensible application of programmable structures to the realization of digital systems cannot take place without computer aided design systems. It is particularly important when the design is intended for novel programmable structures containing LUT-based cells and embedded memory blocks, since traditional methods for technology mapping are oriented towards gate structures and based on minimization and factorization of Boolean functions. This article focuses on finite state machine synthesis including logic optimization techniques, the technology mapping techniques, and the techniques that provide the resulting circuits with concurrent error detection capability. It is shown that a considerably more effective method of synthesis intended for CPLD and FPGA structures is based on the decomposition scheme.

3

Realizacja dekodera adresów z zastosowaniem w pełni określonych funkcji boolowskich

Majchrzyk M., Borowik G., Darakchiev R.

Pomiary Automatyka Kontrola

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2008

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R. 54, nr 8

505-507

PL

Prezentujemy efektywną metodę syntezy w pełni określonych funkcji boolowskich charakteryzujących się dużą dysproporcją występującą na wyjściu. Opisywane funkcje zawierają jedynie mały podzbiór słów dla których wartość jest równa 1. Opracowano specjalny algorytm selekcji takich wektorów. Badania zostały wykonane na układach programowalnych FPGA Stratix firmy Altera. W porównaniu do klasycznych metod syntezy osiągnęliśmy, przy porównywalnym użyciu wbudowanych bloków pamięciowych EMB, redukcję zasobów logicznych LUT - średnio do 95%.

EN

We are proposing a cost-efficient realization scheme for completely-specified logic functions characterized by a huge disproportion. The functions described contain millions of input words but only few of them can give us information. An appropriate method of logic synthesis for identifying mentioned vectors (registered vectors) has been developed. In this method logic functions are implemented using both embedded memory blocks and LUT-based programmable logic blocks available in today's FPGAs. In comparison with the classical logic synthesis methods we have obtained extremely encouraging results: with a comparable number of EMBs, the number of logic cells has been reduced by 95%. The investigation has been implemented using Altera's Stratix devices.

4

Improved state encoding for FSM implementation in FPGA structures with embedded memory blocks

Borowik G.

Electronics and Telecommunications Quarterly

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2008

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Vol. 54, No 1

9-28

EN

Modern FPLD devices have a very complex structure. They combine PLA-like structures as well as FPGA's and even memory-based structures. However, the lack of an appropriate synthesis method does not allow the features of the modern FPLD's to be fully exploited. In this paper, an important problem of state assignment for an FSM as an extension of the previous research on ROM-based FSM implementation is presented. We pinpoint the sources of additional optimization of the functional decomposition and relate them to the state encoding conditions. The method is based on a reduction of a state assignment problem to a graph coloring problem. To this end, the so called multi-graph of incompatibility of memory T-words is applied. As a result, a new design technique for implementation of sequential circuits using embedded memory blocks of FPGA's has been developed. Preliminary experimental results- are extremely encouraging.