This article presents the results of research related to the construction of a complete packet classifier, constituting the main element of a hardware-based firewall security system. The developed solution is based on two filter blocks operating in parallel: address filters and network ports filters. The proposed method of filtering network addresses using dedicated TCAM memory is characterized by fast operational speeds and a much more effective usage of FPGA chip resources as compared to commercial versions offered by Xilinx. Similarly, in order to verify network ports, especially taking into account rules that define port ranges, the authors proposes a novel concept based on cascades of elementary RAM16X1D memory available in Xilinx’s Virtex FPGA family circuits. The resulting data processing speed in excess of 160 million of packets per second, coupled with positive results of preliminary tests, make it possible to use the classification system in modern wide bandwidth telecommunications networks.