Wyniki wyszukiwania - BazTech

1

Sprzętowa implementacja dekodera LDPC w strukturze FPGA*

Kuc Mateusz, Sułek Wojciech, Kania Dariusz

Przegląd Elektrotechniczny

|

2019

|

R. 95, nr 3

58--62

PL

W artykule przedstawiono sprzętową implementację dekodera LDPC (ang. Low-Density Parity-Check) w strukturze FPGA (ang. Field Programmable Gate Array). W celu zredukowania złożoności implementacji wykorzystano algorytm MIN-SUM dla węzłów bitowych (CNU) i węzłów kontrolnych (VNU). W zrealizowanym dekoderze wykorzystano kod regularny (3,6) macierzy kontrolnej o wymiarach 512 x 1024 i zaimplementowano 4-bitową magistralę danych. Poprawność działania dekodera zweryﬁkowano praktycznie.

EN

The article presents the hardware implementation of the LDPC decoder (Low-density parity-check) in the FPGA structure (Field Programmable Gate Array). In order to reduce the complexity of the implementation, the Min-Sum algorithm for bit nodes (CNUs) and control nodes (VNUs) was used. The presented implementation was created using a regular code (3.6) of a 512 x 1024 control matrix. A 4-bit data bus was implement.

2

Problems in solving fractional differential equations in a microcontroller implementation of an FOPID controller

Matusiak Mariusz, Ostalczyk Piotr

Archives of Electrical Engineering

|

2019

|

Vol. 68, nr 3

565--577

EN

The article focuses on the fractional-order backward difference, sum, linear time-invariant equation analysis, and difficulties of the fractional calculus microcontroller implementation with regard to designing a fractional-order proportional integral derivative (FOPID) controller. In opposite to the classic proportional integral derivative (PID), the FOPID controller is defined by five independent parameters. Hence, it is more customizable and, potentially, more precise on condition that the values of fractional integration and differentiation orders are properly selected. However, a number of operations and the time required to calculate the output signal continuously increase. This can be a significant problem considering the limitations of a microcontroller, including memory size and a constant sampling time of the set-up analog-to-digital (ADC) converters. In the article, three solutions are considered, and results obtained in the experiments are presented.

3

Basic Aspects of Designing a High-performance Processor Structure for Calculating a "true" Discrete Fractional Fourier Transform

Cariow A., Majorkowska-Mech D.

Measurement Automation Monitoring

|

2018

|

Vol. 64, No. 2

43--45

EN

This paper presents a basic aspects of structural design of the highperformance processor for implementation of discrete fractional Fourier transform (DFrFT). The general idea of the possibility of parallelizing the calculation of the so-called “true” discrete Fourier transform on the basis of our previously developed algorithmic approach is presented. We specifically focused only on the general aspects of the organization of the structure of such a processor, since the details of a particular implementation always depend on the implementation platform used, while the general idea of constructing the structure of the processor remains unchanged.

4

Efficiency of Spartan-7 FPGA devices in implementation of contemporary cryptographic algorithms

Sugier J.

Journal of Polish Safety and Reliability Association

|

2018

|

Vol. 9, No. 3

75--84

EN

Hardware implementations of cryptographic algorithms are ubiquitous in contemporary computer systems where they are used to ensure appropriate level of security e.g. in high-speed data transmission, authentication and access control, distributed cloud storage, etc.. In this paper we evaluate size and speed efficiency of FPGA implementations of selected popular cryptographic algorithms in the newest cost-sensitive Spartan-7 devices form Xilinx, Inc.. The investigated set of algorithms included four examples: the AES-128 standard symmetric block cipher, the BLAKE-256 hash function and two size variants of the KECCAK-f[b] compression function, b = 400 and 1600, with the larger variant being used as the core of the new SHA-3 standard. The main aim of this research was to provide a uniform and comparable implementation approach for all the ciphers so that the new potentials of the Spartan-7 internal architecture would be put to the test in realization of their specific cryptographic transformations and data distribution. Each of the four algorithms was implemented in five architectures: the basic iterative one (with one instance of the cipher round instantiated in hardware) plus two loop unrolled ones (with two and four or five rounds in hardware) and their two pipelined variants (with registers at the outputs of each round enabling parallel processing of multiple streams of data). Uniform implementation methodology applied to 20 cases of cipher & architecture combinations created a consistent testbed, producing comparable results which allowed to evaluate efficiency of the new hardware platform in implementation of the different algorithms in various unrolled and pipelined organizations.

5

High-performance FPGA Architecture for Data Streams Processing on Example of IPsec Gateway

Korona M., Skowron K., Trzepinski M., Rawski M.

International Journal of Electronics and Telecommunications

|

2018

|

Vol. 64, No. 3

351--356

EN

In modern digital world, there is a strong demand for efficient data streams processing methods. One of application areas is cybersecurity - IPsec is a suite of protocols that adds security to communication at the IP level. This paper presents principles of high-performance FPGA architecture for data streams processing on example of IPsec gateway implementation. Efficiency of the proposed solution allows to use it in networks with data rates of several Gbit/s.

6

An Enhanced Run-Length Encoding Compression Method for Telemetry Data

Shan Y., Ren Y., Zhen G., Wang K.

Metrology and Measurement Systems

|

2017

|

Vol. 24, nr 3

551--562

EN

The telemetry data are essential in evaluating the performance of aircraft and diagnosing its failures. This work combines the oversampling technology with the run-length encoding compression algorithm with an error factor to further enhance the compression performance of telemetry data in a multichannel acquisition system. Compression of telemetry data is carried out with the use of FPGAs. In the experiments there are used pulse signals and vibration signals. The proposed method is compared with two existing methods. The experimental results indicate that the compression ratio, precision, and distortion degree of the telemetry data are improved significantly compared with those obtained by the existing methods. The implementation and measurement of the proposed telemetry data compression method show its effectiveness when used in a high-precision high-capacity multichannel acquisition system.

7

Some Schemes for Implementation of Arithmetic Operations with Complex Numbers Using Squaring Units

Cariow A., Cariowa G.

Measurement Automation Monitoring

|

2017

|

Vol. 63, No. 6

209--211

EN

In this paper, new schemes for a squarer, multiplier and divider of complex numbers are proposed. Traditional structural solutions for each of these operations require the presence of some number of general-purpose binary multipliers. The advantage of our solutions is a removing of multiplications through replacing them by less costly squarers. We use Logan's trick and quarter square technique, which propose to replace the calculation of the product of two real numbers by summing the squares. Replacing usual multipliers with digital squares implies the reducing power consumption as well as decreases the complexity of the hardware circuit. The squarer requiring less area and power as compared to general-purpose multiplier, it is interesting to assess the use of squarers to implementation of complex arithmetic.

8

Design and implementation of improved sliding mode controller on 6R manipulator

Korayem M. H., Nekoo S. R., Khademi A., Abdollahi F.

Journal of Theoretical and Applied Mechanics

|

2017

|

Vol. 55 nr 1

265--280

EN

In this work, we present an improved sliding mode control (ISMC) technique designed and implemented for control of 6R manipulator. Sliding mode control (SMC) is a well-known nonlinear robust method for controlling systems in the presence of uncertainties and disturbances and systems with complex dynamics as in manipulators. Despite this good property, it is difficult to implement this method for the manipulator with a complex structure and more than three degree-of-freedom because of the complicated and massive equation and chattering phenomenon as a property of SMC in control inputs. Here, the chattering phenomenon is eliminated by using an effective algorithm called ISMC and implemented to 6R manipulator by using a low-cost control board based on an ARM microcontroller with high accuracy and memory. The carrying load is considered as the uncertainty for the manipulator, while the dynamic load carrying capacity (DLCC) is considered as a robot performance criterion showing robustness of the controller. The results of simulations and experiments show that the proposed approach has a good performance and is suitable and practical to be applied for manipulators.

9

Sprzętowa realizacja protokołu IPSec w strukturach programowalnych dla sieci multigigabitowych

Korona M., Bieniasz J., Skowron K., Trzepiński M., Rawski M.

Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne

|

2016

|

nr 8-9

724--727

PL

Przedstawiono realizacje bramki protokołu IPSec w układach programowalnych FPGA. Wydajność zaproponowanego rozwiązania umożliwia stosowanie ich w sieciach o szybkościach transmisji rzędu kilku Gbit/s.

EN

The paper presents the implementation of IPSec gateway in FPGA device. Performance of the proposed solution allows to use it in networks with data rates of several Gbit/s.

10

Faster Point Scalar Multiplication on Short Weierstrass Elliptic Curves over Fp using Twisted Hessian Curves over Fp2

Wroński M.

Journal of Telecommunications and Information Technology

|

2016

|

nr 3

98--102

EN

This article shows how to use fast Fp2 arithmetic and twisted Hessian curves to obtain faster point scalar multiplication on elliptic curve ESW in short Weierstrass form over Fp. It is assumed that p and #ESW(Fp) are different large primes, #E(Fq) denotes number of points on curve E over field Fq and #Et SW (Fp), where Et is twist of E, is divisible by 3. For example this method is suitable for two NIST curves over Fp: NIST P-224 and NIST P-256. The presented solution may be much faster than classic approach. Presented solution should also be resistant for side channel attacks and information about Y coordinate should not be lost (using for example Brier-Joye ladder such information may be lost). If coefficient A in equation of curve ESW : y2 =x3+Ax+B in short Weierstrass curve is not of special form, presented solution is up to 30% faster than classic approach. If A=−3, proposed method may be up to 24% faster.

11

Hardware implementation of a decision tree classifier for object recognition applications

Fularz M., Kraft M.

Measurement Automation Monitoring

|

2015

|

Vol. 61, No. 7

379--381

EN

Hardware implementation of a widely used decision tree classifier is presented in this paper. The classifier task is to perform image-based object classification. The performance evaluation of the implemented architecture in terms of resource utilization and processing speed are reported. The presented architecture is compact, flexible and highly scalable and compares favorably to software-only solutions in terms of processing speed and power consumption.

12

Efficiency of FPGA architectures in implementations of AES, Salsa20 and Keccak cryptographic algorithms

Sugier J.

Journal of Polish Safety and Reliability Association

|

2015

|

Vol. 6, No. 2

117--124

EN

The aim of this paper is to test efficiency of automatic implementation of selected cryptographic algorithms in two families of popular-grade FPGA devices from Xilinx: Spartan-3 and Spartan-6. The set of algorithms include the Advanced Encryption Standard (AES) used worldwide as a symmetric cipher along with two hash algorithms: Salsa20 (developed with ECRYPT Stream Cipher Project) and Keccak permutation function (core of the new SHA-3 standard). The ciphers were expressed in 5 architectures: the basic iterative one (one instance of a round in hardware) and its four derivatives created by loop unrolling and pipelining. With each of the architectures implemented in both Spartan devices this gave the total of 30 test cases, which, upon automatic implementation, created a comprehensive and consistent base for comparison of the ciphers, applied architectures and FPGA devices used for implementation.

13

Low-cost hardware implementations of Salsa20 stream cipher in programmable devices

Sugier J.

Journal of Polish Safety and Reliability Association

|

2013

|

Vol. 4, No. 1

121--128

EN

Salsa20 is a 256-bit stream cipher that has been proposed to eSTREAM, ECRYPT Stream Cipher Project, and is considered to be one of the most secure and relatively fastest proposals. This paper describes hardware implementation of various architectures of this cipher in popular Field Programmable Gate Arrays (FPGA). The implemented architectures are based on the loop-unrolled data flow organization and after pipelining they can reach the throughput in the range of 20 – 30 Gbps even after fully automatic implementation in popular low-cost families of Spartan-3 and Spartan-6 from Xilinx. More resource-limited iterative architectures achieve speed of 1 – 2 Gbps. The results that are included in this work present potential of the algorithm when it is implemented in a specific FPGA environment and provide some information for evaluation of cipher effectiveness in contemporary popular programmable devices.

14

Hierarchiczny system sterowania procesem mieszania. Implementacja sprzętowa i badania testowe

Błaszkiewicz K., Biniecki P., Piotrowski R.

Pomiary Automatyka Robotyka

|

2012

|

R. 16, nr 7-8

90-96

PL

Proces mieszania często występuje w różnych gałęziach przemysłu. W artykule rozważane jest sporządzanie mieszaniny aceton-octan etylu. Podstawowym celem jest uzyskanie właściwego stopnia jednorodności mieszaniny. W artykule zbudowano model matematyczny procesu mieszania i zaprojektowano warstwowy system sterowania. Składa się on z nadrzędnego regulatora rozmytego oraz warstwy bezpośredniej z regulatorami typu PID i sterowaniem binarnym. Przeprowadzono badania testowe działania układu sterowania w strukturze sprzętowej i dokonano analizy uzyskanych wyników sterowania.

EN

Mixing process is very often used in many various fields of industry. In this paper the mixture of acetone and ethyl acetate is considered. Desire is to achieve proper homogeneity of mixture. The paper presents mathematical model of mixing process and designed two-layer structure of control system. The fuzzy controller is implemented in upper layer. Direct layer consists of PID controllers and binary control. Control system is tested by simulation for hardware in the loop control system. The control results are analyzed.

15

Analysis of possible system-level hardware implementation of the selected shape description algorithms

Frejlichowski D.

Journal of Theoretical and Applied Computer Science

|

2012

|

Vol. 6, nr 4

51-58

EN

This paper is devoted to the problem of the hardware implementation of selected shape description algorithms. The properties and complexity of particular methods are discussed in order to find those that are most applicable to a direct hardware implementation. Thus, the complexity of both the approaches and the processed data should be minimised. In this paper the properties of the Roundness, X/Y Feret, Point Distance Histogram, UNL, UNL-Fourier and Fourier Descriptors methods were investigated. Two aspects were analysed — the efficiency of an exemplary practical shape analysis application and the time consumption of the implemented algorithms.

16

Implementation of symmetric block ciphers in popular-grade FPGA devices

Sugier J.

Journal of Polish Safety and Reliability Association

|

2012

|

Vol. 3, No. 2

179--188

EN

In this paper we discuss hardware implementations of the two best ciphers in the AES contest – the winner Rijndael and the Serpent – in low-cost, popular Field-Programmable Gate Arrays (FPGA). After presenting the elementary operations of the ciphers and organization of their processing flows we concentrate on specific issues of their implementations in two selected families of popular-grade FPGA devices from Xilinx: currently the most common Spartan-6 and its direct predecessor Spartan-3. The discussion concentrates on differences in resources offered by these two families and on efficient implementation of the elementary transformations of the two ciphers. For case studies we propose a selection of different architectures (combinational, pipelined and iterative) for the encoding units and, after their implementation, we compare size requirements and performance parameters of the two ciphers across different architectures and on different FPGA platforms.

17

Sprzętowa implementacja algorytmu maskowania zakłóceń transmisji cyfrowych danych wizyjnych

Zając W., Andrzejewski G.

Przegląd Elektrotechniczny

|

2011

|

R. 87, nr 11

186-190

PL

W artykule przedstawiono wyniki prac nad sprzętową implementacją algorytmu maskowania zakłóceń transmisji cyfrowych danych wizyjnych. Przedstawiono założenia algorytmu, opisano mechanizmy maskowania zakłóceń, zaproponowano strategię implementacji oraz przedyskutowano wyniki.

EN

In the paper there are presented results of work on hardware implementation of digital image data transmission error concealment algorithm. The idea of transmission error concealment of visual data is presented and discussed, Hybrid Error Concealment Algorithm (HECA) operation and structure is described. Considered elements (operational stages) of the HECA algorithm are described in detail. Implementation strategy and results are presented and a conclusion is drawn.

18

Implementacja w układzie reprogramowalnym wieloprocesorowego systemu realizującego algorytm RANSAC

Fularz M., Kraft M.

Pomiary Automatyka Kontrola

|

2011

|

R. 57, nr 8

914-916

PL

W artykule opisano programową, wieloprocesorową realizację algorytmu RANSAC, który umożliwia odporną estymację modelu matematycznego z danych pomiarowych zawierających znaczący odsetek wartości odstających (ang. outliers). System został zaimplementowany w układzie FPGA w oparciu o konfigurowalne soft procesory MicroBlaze. W pracy przedstawiono opis algorytmu RANSAC, sposób jego podziału w celu przetwarzania równoległego, a także proces konfiguracji systemu wieloprocesorowego. Zaprezentowano również przyrost prędkości przetwarzania w zależności od liczby zastosowanych rdzeni procesorowych, porównano te wyniki do realizacji na komputerze klasy PC i przedstawiono zużycie zasobów układu FPGA.

EN

The paper describes a multiprocessor system implementing the RANSAC algorithm [3] which enables robust estimation of a fundamental matrix from a set of image keypoint correspondences containing some amount of outliers. The fundamental matrix encodes the relationship between two views of the same scene. The knowledge of the fundamental matrix enables e.g. the reconstruction of the scene structure. The implemented system is based on three MicroBlaze microprocessors [5] (one master, two slaves) and a dedicated hardware coprocessor connected using fast simplex link (FSL) interfaces [6]. The slave microprocessors perform the task of fundamental matrix computation from point correspondences using singular value decomposition - the so called 8-point algorithm [1, 2] (hypothesis generation). The master processor, along with the connected coprocessor, is responsible for dataflow handling and hypothesis testing using the Sampson error formula (7). The hypothesize and test framework used in RANSAC allows for largely independent task execution. The design is a development of a system described in [5]. The block diagram and dataflow diagram of the proposed solution are given in Figs. 1 and 2, respectively. Tabs. 1 and 2 summarize the use of FPGA resources. With a 100 MHz clock, the designed system is capable of processing the data at the speed which is roughly equivalent to that of the Atom N270 microprocessor clocked at 1,2 GHz. The resulting solution will be targeted at applications for which small size, weight and power consumption are critical. The design is also easily scalable - addition of more slave processors will result in additional increase in the processing speed.

19

Computationally efficient methods of approximations of the S-shape functions for image processing and computer graphics tasks

Cyganek B., Socha K.

Image Processing & Communications

|

2011

|

Vol. 16, no 1-2

19-28

EN

The paper describes a number of methods for approximation of the S-shape functions, frequently used in computer graphics or image processing. The main focus is on efficient software and hardware implementations. We present original code for the high and low level languages which implement different approximations of the S-shape functions. Additionally we introduce the FixedFor <> template class which fills the gap of efficient representation of different length fixed-point data formats in C++.

20

Implementacja algorytmu SOSEMANUK w strukturze FPGA

Kaczyński K.

Biuletyn Wojskowej Akademii Technicznej

|

2011

|

Vol. 60, nr 3

391-414

PL

W artykule przedstawiono implementację algorytmu SOSEMANUK w strukturze FPGA Altera Stratix II. Przedstawiona została specykacja algorytmu wraz z charakterystyką bezpieczeństwa. Wykonano analizę możliwości implementacji, zajętości zasobów oraz wydajności algorytmu SOSEMANUK w przedstawionej platformie sprzętowej. Wykonane zostało porównanie uzyskanych wyników z algorytmami profilu sprzętowego konkursu eSTREAM oraz z przedstawioną przez twórców implementacją programową.

EN

In the paper implementation of SOSEMANUK stream cipher in FPGA structure Altera Stratix II was described. Specication and security of algorithm was also presented. Analysis of implementation possibility resources usage and efficiency of SOSEMANUK FPGA implementation was made. Paper contains comparison of obtained results with other algorithms implementations of eSTREAM contest hardware profile and with software implementation made by authors of SOSEMANUK.