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High-speed FPGA pipelined binary-to-residue converter

Czyżak M., Smyk R.

Poznan University of Technology Academic Journals. Electrical Engineering

2008

No 58

65-72

An architecture and the FPGA realization of a high-speed pipelined binary-to-residue converter for five-bit moduli are presented. The converter algorithm is based on segmentation of the input binary word into segments of at most five-bit length. For the number represented by each segment modulo m reduction is performed. The obtained residues are added by using the multi-operand modulo adder m based on the carry-save adder (CSA) tree, reduction of the number represented by the output CSA tree vectors to 2m range and fast two-operand modulo m adder.