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1

The low-area FPGA design for the post-quantum cryptography proposal Round5

Andrzejczak Michał

Annals of Computer Science and Information Systems

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2019

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Vol. 18

213--219

EN

Post-Quantum Cryptography (PQC) is getting attention recently. The main reason of this situation is the announcement by the U.S. National Institute for Standard and Technology (NIST) about an opening of the standardization process for PQC. Recently NIST published a list of submissions qualified to the second round of this process. One of the selected algorithms is Round5, offering a key encapsulation mechanism (KEM) and public key encryption (PKE). Due to high complexity of post-quantum cryptosystems, only a few FPGA implementations have been reported to date. In this paper, we report results for low-area purely-hardware implementation of Round5 targeting low-cost FPGAs.

2

Synthesis of the configuration structure of digital receiver of NQR radiospectrometer

Hotra O., Samila A., Politansky L.

Przegląd Elektrotechniczny

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2018

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R. 94, nr 7

58--61

EN

Analysis of methods for demodulation of free induction decay signal that are suitable for use in pulsed nuclear quadruple resonance radiospectrometers was performed. The structure and MATLAB Simulink model of the receive path of radiospectrometer was synthesized, in which the Software Defined Radio technology was chosen for the implementation of a quadrature detector with a filtration and quadrature reflection suppression system. The application of the principle of direct digitization of the signal made it possible to significantly reduce the length of the analog portion of the receiver, and, consequently, reduce the noise of the useful signal and the level of out-of-band higher order spectral components.

PL

Przeprowadzono analizę metod demodulacji sygnału zaniku indukcji swobodnej, które są odpowiednie do stosowania w impulsowych radiospektrometrach jądrowego rezonansu kwadrupolowego. Opracowano strukturę i model ścieżki odbiorczej radiospektromeru w środowisku MATLAB Simulink, w którym do realizacji kwadraturowego detektora z układem filtracji i tłumienia odbicia kwadraturowego wybrano oprogramowanie Software Defined Radio. Zastosowanie zasady bezpośredniej cyfryzacji sygnału pozwoliło znacznie zmniejszyć długość analogowej części odbiornika, a w konsekwencji zmniejszyć szum sygnału użytecznego oraz poziom pozapasmowych składowych widmowych wyższych rzędów.

3

Comparison of three different 2-D space vector PWM algorithms and their FPGA implementations

Bishuang F., Guanzheng T., Shaosheng F.

Journal of Power Technologies

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2014

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Vol. 94, nr 3

176--189

EN

To improve the flexibility of the multilevel space vector pulse width modulation (SVPWM), various algorithms have been developed. A theoretical comparison is made for three 2-D SVPWM algorithms: they are g-h frame, α' - β' frame and multilevel SVPWM based on two-level (α* - β* frame). The aim is to provide a guideline for the selection of the most appropriate SVPWM technique for digital implementation. Among them, the α' - β' frame offers the best flexibility with the least calculation and is well suited for digital implementation. The α* - β* frame is the most intuitionistic but has the largest calculation. New general methods of the g-h frame and α' - β' frame for any level SVPWM are also provided, which needs only the angle θ and the modulation depth m to generate and arrange the final vector sequence. All three methods are implemented in a field programmable gate array (FPGA) with very high speed integrated circuit hardware description language (VHDL) and compared in terms of implementation complexity and logic resources required. Simulation results show the absolute advantages of α' - β' frame in briefness and resources use. Finally, an experimental test result is presented with a three-level neutral-point-clamped (NPC) inverter.

4

Reconfigurable General-purpose Processor Idea Overview

Zarzycki I

International Journal of Microelectronics and Computer Science

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2013

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Vol. 4, nr 1

37--42

EN

This paper presents the idea of the reconfigurable general-purpose processor implemented as dynamically reconfigurable FPGA (called “reconfigurable processor” in the rest of this document). Proposed solution is compared with currently available general-purpose processors performing instructions sequentially (called “sequential processors” in the rest of this paper). This document presents the idea of such reconfigurable processor and its operation without going into implementation details and technological limitations. The main novelty of reconfigurable processor lays in lack of typical for other processors sequential execution of instructions. All operations (if only possible) are executed in parallel, in hardware also at subistruction level. Solution proposed in this paper should give speed up and lower power consumption in comparison with other processors currently available. Additionally proposed architecture does not requires neither any modifications in source codes of already existing, portable programs nor any changes in development process. All of the changes can be performed by compiler at the stage of compilation.

5

FPGA implementations of low precision floating point multiply-accumulate

Amaricai A., Boncalo O., Sicoe O

International Journal of Microelectronics and Computer Science

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2013

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Vol. 4, nr 4

159--163

EN

Floating point (FP) multiply-accumulate (MAC) represents one of the most important operations in a wide range of applications, such as DSP, multimedia or graphic processing. This paper presents a FP MAC half precision (16-bit) FPGA implementation. The main contribution of this work is represented by the utilization of modern FPGA DSP block for performing both mantissa multiplication and mantissa accumulation. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on one of the multiplicand, and, a left shift for the other. This results in efficient DSP usage; thus both cost savings and higher performance (high working frequencies and low latencies) are targeted for MAC operations.

6

Calibration of a mixed-signal power network transient stability analysis emulator

Lanz G, Fabre L., Lilis G, Kyriakidis T, Sallin D, Cherkaoui R., Kayal M.

International Journal of Microelectronics and Computer Science

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2013

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Vol. 4, nr 4

142--147

EN

The emerging ﬁeld of power system emulation for real time smart grid management is very demanding in terms of speed and accuracy. This paper provides detailed information about the electronics calibration process of a high-speed power network emulator dedicated to the transient stability analysis of power systems. This emulator uses mixed-signal hardware to model the dynamic behavior of a power network. Special design allows the self-calibration of the analog electronics through successive measurements and correction steps. The calibration operation guarantees high resolution of the transient stability analysis results, so that they can be reliably used for operational planning and control on real power networks.

7

Polyphase Comb Filter Based on Dispatching Input Bit-stream and Interlaying Multiplexer Techniques for Sigma-Delta ADCs

Abdollahvand S., Goes J., Paulino N., Gomes L.

International Journal of Microelectronics and Computer Science

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2012

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Vol. 3, nr 4

152-158

EN

This paper describes a new design approach for implementing a Polyphase Comb Filter (PCF) based on dispatching input bit-stream and interlaying multiplexer techniques. In order to make our solution more energy efficient in comparison with prior art, we start with a detailed analysis of the drawbacks and advantages of the existing classical techniques. A new structure based on a novel SINC3 design is proposed. This new design uses a controller unit to activate one sub-filter in each specific time interval. As a consequence, no input registers and switches are required. Since this decimation filter is working with a single-bit output bit-stream, the required multiplication function can be simply done by using interlaying multiplexers (MUXs). By interlaying different levels of MUXs along with the navigation of the input bit stream we can easily emulate the multiplication operation. The implementation in a Xilinx Spartan3 FPGA demonstrates the feasibility and hardware efficiency of our solution . The proposed new filter architecture can be readily applicable to any Sigma-Delta (ΣΔ) ADC with a single-bit output stream and it requires a reduced number of adders and registers when compared with the state-of-the-art approaches.

8

Projekt i implementacja sterowników karty graficznej VGA w układach FPGA

Niemojewski M., Sapiecha P.

Pomiary Automatyka Kontrola

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2007

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R. 53, nr 7

81-83

PL

Celem pracy jest zaprojektowanie interfejsu graficznego i tekstowego umożliwiającego prezentacje informacji na ekranie monitora VGA wykorzystując technologie logicznych układów programowalnych, napisanie sterowników sprzętu dla systemu operacyjnego žClinux oraz przeprowadzenie i analiza wyników testów uzyskanego rozwiązania ze względu na parametry: prędkość rysowania obrazu, stopień obciążenia pamięci.

EN

The paper presents design and implementation of the text and graphics interface for FPGA based system. The article describes VHDL module and video graphics driver for žClinux operating system. The article describes tests of the device. The paper presents possible future work for the design.