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1

FPGA implementations of low precision floating point multiply-accumulate

Amaricai A., Boncalo O., Sicoe O

International Journal of Microelectronics and Computer Science

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2013

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Vol. 4, nr 4

159--163

EN

Floating point (FP) multiply-accumulate (MAC) represents one of the most important operations in a wide range of applications, such as DSP, multimedia or graphic processing. This paper presents a FP MAC half precision (16-bit) FPGA implementation. The main contribution of this work is represented by the utilization of modern FPGA DSP block for performing both mantissa multiplication and mantissa accumulation. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on one of the multiplicand, and, a left shift for the other. This results in efficient DSP usage; thus both cost savings and higher performance (high working frequencies and low latencies) are targeted for MAC operations.

2

Hierarchical residue number systems with small moduli and simple converters

Tomczak T.

International Journal of Applied Mathematics and Computer Science

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2011

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Vol. 21, no 1

173-192

EN

In this paper, a new class of Hierarchical Residue Number Systems (HRNSs) is proposed, where the numbers are represented as a set of residues modulo factors of 2k š 1 and modulo 2k. The converters between the proposed HRNS and the positional binary number system can be built as 2-level structures using efficient circuits designed for the RNS (2k - 1, 2k, 2k +1). This approach allows using many small moduli in arithmetic channels without large conversion overhead. The advantages resulting from the use of the proposed HRNS depend on the possibility of factorisation of moduli [...].

3

Mnożenie o stałej szerokości bitowej z zaokrąglaniem

Jamro E., Wielgosz M., Russek P., Wiatr K.

Pomiary Automatyka Kontrola

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2010

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R. 56, nr 7

769-771

PL

Niniejszy artykuł prezentuje mnożenie o stałej szerokości bitowej, dla którego szerokość bitowa argumentów jest taka sama jak danej wyjściowej. Najmłodsze bity wyniku są odrzucane już na etapie mnożenia, dzięki czemu układ zajmuje mniej zasobów kosztem niewielkiego błędu obliczeń, który można zmniejszyć poprzez zastosowanie dodatkowych bitów ochronnych, układu kompensacji błędu oraz operacji zaokrąglania. Niniejszy artykuł proponuje nową architekturę uwzględniające powyższe operacje.

EN

The paper deals with fixed-width multipliers, i.e. multipliers for which inputs and output bit-width is the same. In order to reduce hardware requirements for such a multiplier, some of the multiplier logic is truncated during multiplication process (see Fig. 1). This, however, introduces a calculation error which can be reduced by both special truncation-error compensation logic (e.g. presented in Fig. 2) and by additional guard bits. As presented in Tabs. 1 and 2, for relatively small number of guard bits g, the overall error is determined by the rounding process rather than truncation. Nevertheless, as it is proved in this paper, for g>0, the error compensation logic interfere with the rounding process, e.g. offsets the Mean Error (ME). Therefore a novel multiplier denoted as Mean Error optimized Rounded Truncated Multiplier (MERTM) is presented. The MERTM, instead of rounding, includes additional AND gates in comparison to the VCTM [1]. As a result, for the MERTM, ME approaches zero.