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1

Exploring Processor Parallelism: Estimation Methods and Optimization Strategies

Jordans R, Corvino R, Jóźwiak L., Corporaal H

International Journal of Microelectronics and Computer Science

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2013

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Vol. 4, nr 2

55--64

EN

Automatic optimization of application-specific instruction-set processor (ASIP) architectures mostly focuses on the internal memory hierarchy design, or the extension of reduced instruction-set architectures with complex custom operations. This paper focuses on very long instruction word (VLIW) architectures and, more specifically, on automating the selection of an application specific VLIW issue-width. The issue- width selection strongly influences all the important processor properties (e.g. processing speed, silicon area, and power consumption). Therefore, an accurate and efficient issue-width estimation and optimization are some of the most important aspects of VLIW ASIP design. In this paper, we first compare different methods for the estimation of required the issue-width, and subsequently introduce a new force-based parallelism estimation method which is capable of estimating the required issue-width with only 3% error on average. Furthermore, we present and compare two techniques for estimating the required issue-width of software pipelined loop kernels and show that a simple utilization-based measure provides an error margin of less than 1% on average.

2

Overlapped filtered multitone modulation and its optimization on VLIW DSP

Silhavy P., Krajsa O., Systel P., Koutny M.

Przegląd Elektrotechniczny

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2011

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R. 87, nr 12a

145-149

EN

In recent years, the multicarrier modulations (MCM) have been applied to wire and wireless transmission systems. MCM enable a nearperfect utilization of the provided frequency band on metallic cables and they also effectively eliminate multipath propagation in terrestrial transmission. They are mainly the implementations called Discrete MultiTone (DMT) and Orthogonal Frequency Division Multiplexing (OFDM). These approaches have also disadvantages, which have led to seeking new approaches to the implementation of the MCM modulation scheme. One of them is the Filtered MultiTone Modulation (FMT). In the article, the channel equalization in overlapped and non-overlapped FMT modulation will be compared. The optimal implementation of FMT on the VLIW DSP will be introduced in the second part.Optimized implementation of filter bank with the help of parallel processing is described, and also frame writing/reading and its synchronization are introduced.

PL

W ostatnich latach, w modulacjach multicarrier (MCM) zostały zastosowane systemy transmisji przewodowej i bezprzewodowej. MCM umożliwiają niemal perfekcyjne wykorzystanie pasma częstotliwości przewidziane w kablach a również skutecznie wyeliminować wielodrogowość w transmisji naziemnej. Są to przede wszystkim implementacje o nazwie Discrete wielotonowy (DMT) i Orthogonal Frequency Division Multiplexing (OFDM). Metody te mają także wady, które doprowadziły do poszukiwania nowych sposobów podejściacia do wdrożenia systemu modulacji MCM. Jednym z nich jest filtrowane wielotonowe modulacji (FMT). W drugiej częścici artykułu została opisana optymalna implementacja modulacji FMT. Wykorzystano bank filtrów z równoległym przetwarzaniem, oraz odpowiednie ramki zapisu/odczytu oraz synchronizacji.

3

CLP approach to optimal instruction scheduling for VLIW processors

Domagała Ł.

Archives of Control Sciences

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2009

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Vol. 19, no. 2

127-149

EN

Along with modern processor architectures where multiple functional units can execute instructions in parallel and numerous resources have to be managed, there is a need for efficient tools facilitating code generation and enhancing development. The aim is to achieve maximal instruction throughput. This is a place where automatic optimization techniques should be employed due to high complexity of the real life problems. This article presents an approach to optimal instruction scheduling for very long instruction word (VLIW) processors using a constraint logic programming (CLP) solver with particular emphasis on the modulo scheduling technique. Modulo scheduling is an optimization technique used to achieve greater instruction level parallelism than one achievable by just optimally scheduling code basic blocks.