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1

Compact terahertz devices based on silicon in CMOS and BiCMOS technologies

But Dmytro B., Chernyadiev Alexander V., Ikamas Kęstutis, Kołaciński Cezary, Krysl Anastasiya, Roskos Hartmut G., Knap Wojciech, Lisauskas Alvydas

Opto-Electronics Review

|

2023

|

Vol. 31, No. 2

art. no. e144599

EN

This paper reports on compact CMOS-based electronic sources and detectors developed for the terahertz frequency range. It was demonstrated that with the achievable noise-equivalent power levels in a few tens of pW/√Hz and the emitted power in the range of 100 μW, one can build effective quasi-optical emitter-detector pairs operating in the 200–266 GHz range with the input power-related signal-to-noise ratio reaching 70 dB for 1 Hz-equivalent noise bandwidth. The applicability of these compact devices for a variety of applications including imaging, spectroscopy or wireless communication links was also demonstrated.

2

Design of 8T SRAM using 14nm FINFET Technology

Vemula Panduranga, Dhar Rudra Sankar

Przegląd Elektrotechniczny

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2022

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R. 98, nr 10

40--43

EN

FinFETs are superior to CMOS because of their low power consumption and ability to function at low voltage. The power consumption of today's digital systems has grown due to an exponential increase in transistor count. Furthermore, due to short channel effects, the performance of typical CMOS devices degrades at lower technology nodes. In sub-14 nm technology, FinFETs have greater control over a gate and outperform CMOS designs. FinFET devices feature a greater Ion current and better extensibility than typical CMOS devices. The quasi planar FinFET structure's simple production technique drew a lot of attention. Static leakage current is decreased by up to 90%, and it is more compact. Because of its area of performance, reduced leakage power, intra-die variability, and lower retention voltages, it is employed more than other FETs in SRAM cell design. In this work, an 8-bit SRAM is built and made in FinFET 14nm, the time delay for read and write operations are computed, as well as the leakage power for the design, and the performance is compared to existing technology.

PL

FinFET są lepsze od CMOS ze względu na niski pobór mocy i zdolność do pracy przy niskim napięciu. Zużycie energii przez dzisiejsze systemy cyfrowe wzrosło z powodu wykładniczego wzrostu liczby tranzystorów. Ponadto, ze względu na efekty krótkich kanałów, wydajność typowych urządzeń CMOS spada w węzłach o niższej technologii. W technologii poniżej 14 nm FinFET mają większą kontrolę nad bramką i przewyższają konstrukcje CMOS. Urządzenia FinFET charakteryzują się większym prądem jonów i lepszą rozciągliwością niż typowe urządzenia CMOS. Prosta technika produkcji quasi-planarnej struktury FinFET przyciągnęła wiele uwagi. Statyczny prąd upływu jest zmniejszony nawet o 90% i jest bardziej kompaktowy. Ze względu na swój obszar działania, zmniejszoną moc upływu, zmienność wewnątrz matrycy i niższe napięcia retencji, jest on stosowany częściej niż inne tranzystory FET w projektowaniu ogniw SRAM. W tej pracy zbudowano i wykonano 8-bitową pamięć SRAM w technologii FinFET 14nm, oblicza się opóźnienie czasowe dla operacji odczytu i zapisu, a także moc upływu dla projektu, a wydajność porównuje się z istniejącą technologią.

3

CMOS single input multiple output universal biquad filter current-mode using only OTAs

Nonthaputha Thanat, Kumngern Montree

Przegląd Elektrotechniczny

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2021

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R. 97, nr 11

64--68

EN

This paper presents a new single-input multiple-output universal biquad filter in current-mode with only four operational transconductance amplifiers (OTAs) and two grounded capacitors. The proposed filter can be obtained all filtering functions, low-pass, high-pass, band-pass, bandstop and all-pass filter that the transfer functions of the filter can be selected by choosing appropriate current output without any component matching conditions. The natural frequency and quality factor of all filtering functions can be controlled electronically and orthogonally using the bias currents of transconductance amplifiers. The active and passive sensitivities of the filters are low. The proposed filter has been simulated using 0.18 µm CMOS process from TSMC. PSPICE simulation results are included to confirm workability of the proposed circuits.

PL

W niniejszym artykule przedstawiono nowy uniwersalny filtr biquad z pojedynczym wejściem i wieloma wyjściami w trybie prądowym z zaledwie czterema wzmacniaczami transkonduktancyjnymi (OTA) i dwoma uziemionymi kondensatorami. W proponowanym filtrze można uzyskać wszystkie funkcje filtrowania, dolnoprzepustowy, górnoprzepustowy, pasmowoprzepustowy, pasmowy i wszechprzepustowy, dzięki czemu funkcje przenoszenia filtra można wybrać poprzez wybór odpowiedniego wyjścia prądowego bez żadnych warunków dopasowania komponentów . Naturalną częstotliwość i współczynnik jakości wszystkich funkcji filtrowania można kontrolować elektronicznie i ortogonalnie za pomocą prądów polaryzacji wzmacniaczy transkonduktancyjnych. Aktywna i pasywna czułość filtrów jest niska. Proponowany filtr został zasymulowany przy użyciu procesu CMOS 0,18 µm firmy TSMC. Zawarto wyniki symulacji PSPICE, aby potwierdzić wykonalność proponowanych obwodów.

4

Dynamic comparator design in 28 nm CMOS

Kaczmarczyk Piotr, Kmon Piotr

International Journal of Microelectronics and Computer Science

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2018

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Vol. 9, nr 4

149--154

EN

The paper presents a dynamic comparator design in 28 nm CMOS process. The proposed comparator is a main block of an asynchronous analog-to-digital converter used in a multichannel integrated circuit dedicated for X-ray imaging systems. We provide comparator’s main parameters analysis, i.e. voltage offsets, power consumption, response delay, and input-referred noise in terms of its dimensioning and biasing. The final circuit occupies 5×5 μm2 of area, consumes 17.1 fJ for single comparison with 250 ps of propagation delay, and allows to work with 4 GHz clock signal.

5

CMOS ECCCII with Linear Tune of Rx and Its Application to Current-Mode Multiplier

Sakul C.

International Journal of Electronics and Telecommunications

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2018

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Vol. 64, No. 3

385--390

EN

In this paper, the second-generation CMOS currentcontrolled-current-conveyor based on differential pair of operational transconductance amplifier has been researched and presented. Since the major improvement of its parasitic resistance at x-port can be linearly controlled by an input bias current, the proposed building block is then called “The Second-Generation Electronically-tunable Current-controlled Current Conveyor” (ECCCI). The applications are demonstrated in form of both 2 quadrant and 4 quadrant current-mode signal multiplier circuits. Characteristics of the proposed ECCCII and its application are simulated by the PSPICE program from which the results are proved to be in agreement with the theory.

6

Upgraded low voltage analog Current-to-Voltage converter with negative feedback

Wojtyna R.

International Journal of Microelectronics and Computer Science

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2017

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Vol. 8, nr 2

80--84

EN

In this paper, an improved version of a current to voltage (C-V) converter is proposed. As compared to the previous version, the number of used transistors has been reduced by 1 and equals 7. The main results of this change are: an improvement of the circuit transfer function linearity, reduction the converter input resistance and decrease of the required supply voltage. Improvements in the considered converter results not only from the reduction of the number of the used transistors but also from the proposed realization of the feedback loop. In this way, it was possibly to get a strong loop gain. As a results, the achieved minimum supply voltage has been reduces from 2V, in case of the previous published converter version, to as low level as 1.2 V, in the case of the newly proposed solution. As for the linearity of the C-V transfer function, apart from its strong loop gain, an important role play also output transistors operating in a small drain to source region (linear region). Working in this region, one obtains a quasi linear voltage to current relationship. The theoretical and simulation results are in a good agreement and are promising.

7

Phaseone 190 MP aerial system: camera design principles and productivity analysis

Raizman Y.

Archiwum Fotogrametrii, Kartografii i Teledetekcji

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2017

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Vol. 29

137--146

EN

Phase One next generation iXU-RS1900 aerial system is based on 100MP medium format camera. It comprises two 90 mm lenses and two CMOS image sensors with pixel size of 4.6 μm shifted outward according to the optical axis of the lenses. Each lens is vertically oriented, providing nadir images with an equal ground resolution. The two stitched images form a large frame with 16,470 pixels across the flight line and 11,570 pixels along the flight providing 190 MP image. The total FOV across flight line is 45.7 deg and FOV along flight line is 33 deg. Productivity analysis for aerial survey cameras may be expressed as an aerial survey productivity (image coverage per hour of flight), distance between flight lines, time required to fly AOI (Area of Interest), or number of flight lines per AOI. The new iXU-RS1900 camera enables an increase in the distance between flight lines and improves aerial survey productivity by 43%. It needs only 34 min of flight to cover the central area of most cities in Europe. Thus, with the new CMOS sensor and short exposure time, high quality aerial imagery may be reached without using an FMC technique.

PL

Kamera lotnicza nowej generacji firmy Phase One iXU-RS190 bazuje na kamerze średnioformatowej 100MP. Łączy dwa obiektywy 90 mm i dwa przetworniki obrazu CMOS z pikselem 4.6 m, przesunięte na zewnątrz względem osi obiektywów. Każdy obiektyw ma pionowo zorientowaną oś, co daje jednakową rozdzielczość terenową zdjęć. Dwa połączone obrazy tworzą kadr o 16 470 pikselach w poprzek i 11 570 pikselach wzdłuż lotu, łącznie o rozdzielczości 190 Mpix. Odpowiada to kątom widzenia 45.7 i 33 odpowiednio w poprzek i wzdłuż lotu. Analiza wydajności kamer lotniczych może być wyrażana jako wydajność obrazowania (powierzchnia kryta zdjęcia na godzinę lotu), odległość między szeregami, czas lotu konieczny na pokrycie obszaru zainteresowania, czy liczbą szeregów na takim obszarze. Nowa kamera iXU-RS190 umożliwia zwiększenie odległości między szeregami i poprawia wydajność o 43%. Potrzebuje tylko 34 minuty lotu na pokrycie centralnej części większości miast europejskich. Z nowym przetwornikiem CMOS i krótkimi ekspozycjami wysoka jakość zdjęć lotniczych może być osiągnięta bez konieczności stosowania technik kompensacji rozmazania (FMC).

8

Identification of ultrasonic frequency for water mist generation using piezoelectric transducer

Senthil Murugan S., Vijayakumar P.

Archives of Materials Science and Engineering

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2017

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Vol. 83, nr 2

74--78

EN

Purpose: Water is the most commonly used medium for fire extinguishing. It is both cheap and has high latent heat of evaporation. But the volume of water required for extinguishing the fire is significantly high, this in turn increases the amount of water stored. This can be reduced significantly by improving the efficiency of the extinguishing action by fire suppression. Water mist fire suppression system, Water mist fire extinguisher, fire hydrant are some of the commonly available methods for fire extinguishment process. This paper is about investigation on ultrasonic frequency for water mist generation without pressurized system. Design/methodology/approach: This technique helps reduce the usage of water required for fire extinguishment to a minimum level. Here H-bridge circuit has been designed with piezoelectric transducer which will operate at various frequency range (0 to 3 MHz). The developed model has been used to predict the minimum frequency required for water mist formation, which is about 2 MHz. Findings: An electrical circuit with h-bridge circuit and piezoelectric transducer has been specifically designed for water mist formation using ultrasonic vibrator has been fabricated. It is a tunable frequency circuit. The tunable frequency range various up to maximum of 3 MHz. From the above experimentation it has been identified that minimum 2 MHz Frequency is required for water mist formation in the water reservoir. Future research in this technique for water mist formation with high rating and increase in number of PET could provide better results. Fine water droplet is also possible with high rating frequency. Research limitations/implications: The developed model has been used to predict the minimum frequency required for water mist formation, which is about 2 MHz. These results will be useful in optimizing the water mist suppression system by varying the frequency and distance from the flame.

9

On-chip current-mode approach to thwart CPA attacks in CMOS nanometer technology

Bellizia D., Scotti G., Trifiletti A.

International Journal of Microelectronics and Computer Science

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2016

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Vol. 7, nr 4

147--156

EN

The protection of information that reside in smart devices like IoT nodes is becoming one of the main concern in modern design. The possibility to mount a non-invasive attack with no expensive equipment, such as a Power Analysis Attack (PAA), remarks the needs of countermeasures that aims to thwart attacks exploiting power consumption. In addition to that, designers have to deal with demanding requirements, since those smart devices require stringent area and energy constraints. In this work, a novel analog-level approach to counteract PAA is presented, taking benefits of the current-mode approach. The kernel of this approach is that the information leakage exploited in a PAA is leaked through current absorption of a cryptographic device. Thanks to an on-chip measuring of the current absorbed by the cryptographic logic, it is possible to generate an error signal. Throughout a current-mode feedback mechanism, the data-dependent component of the overall consumption can be compensated, making the energy requirement constant at any cycle and thwarting the possibility to recover sensible information. Two possible implementations of the proposed approach are presented in this work and their effectiveness has been evaluated using a 40nm CMOS design library. The proposed approach is able to increase the Measurements to Disclosure (MTD) of at least three orders of magnitude, comparing to the unprotected implementation. It has to be pointed out that the on-chip current-mode suppressor, based on the proposed approach, is able to provide a very good security performance, while requiring a very small overhead in terms of silicon area (xl.007) and power consumption (xl.07).

10

On analog comparators for CMOS digital pixel applications. A comparative study

Jendernalik W.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2016

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Vol. 64, nr 2

271--278

EN

Voltage comparator is the only - apart from the light-to-voltage converter - analog component in the digital CMOS pixel. In this work, the influence of the analog comparator nonidealities on the performance of the digital pixel has been investigated. In particular, two versions of the digital pixel have been designed in 0.35 μm CMOS technology, each using a different type of analog comparator. The properties of both versions have been compared. The first pixel utilizes a differential comparator with the increased size and improved electrical performance. The second structure is based on a very simple non-differential comparator with a reduced size and degraded performance. Theoretical analysis of the comparator nonideality effect on the quality of the image obtained from the digital pixel matrix as well as simulation results are provided.

11

Prosty komparator analogowydla cyfrowego przetwornika obrazu CMOS

Jendernalik W.

Przegląd Elektrotechniczny

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2015

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R. 91, nr 9

85-88

PL

Komparator napięciowy, oprócz przetwornika światło-napięcie, jest jedynym elementem analogowym w cyfrowym pikselu CMOS. W pracy badano wpływ nieidealności komparatora analogowego na parametry cyfrowego piksela. W tym celu zaprojektowano w technologii CMOS 0,35 μm dwie wersje cyfrowego piksela, różniące się typem zastosowanego komparatora analogowego. W pierwszej wersji piksela zastosowano różnicowy komparator o zwiększonej powierzchni topografii i polepszonych własnościach elektrycznych. W drugiej wersji zastosowano bardzo prosty nieróżnicowy komparator o zmniejszonej powierzchni i gorszych własnościach elektrycznych. Przedstawiono analizę teoretyczną wpływu nieidealności komparatora na jakość obrazu (szum typu FPN) uzyskiwanego z matrycy cyfrowych pikseli i przedstawiono wyniki symulacji komputerowych.

EN

A voltage comparator, in addition to the light-to-voltage converter, is the only analogue part of the CMOS digital pixel. In this work, the influence of an analogue comparator nonidealities on the digital pixel’s parameters was investigated. For this purpose, it was designed in 0.35 μm CMOS technology two versions of the digital pixel, which differ in the type of an analogue comparator used. In the first version of the pixel is used a differential comparator with a larger layout area and an improved electrical parameters. In the second version, is used a very simple single-ended comparator with a reduced layout area and a worse electrical properties. The analytical analysis of the influence of a comparator nonidealities on an image quality (FPN noise) from the array of the digital pixels is presented. The simulation results are also presented.

12

Evolution of Low Drop Out Voltage Regulator in CMOS Technologies

Mustafa N. B., Amin S., Reaz M. B. I., Hashim F. H., Kamal N.

Przegląd Elektrotechniczny

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2015

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R. 91, nr 12

26-33

EN

The demand for low voltage devices has initiated the development of Low Drop Out (LDO) regulator in manifold. This paper presents a review of various LDO frameworks that have been implemented in CMOS technologies and the impact of frameworks related to the parameters of the LDO. The LDO architecture is evaluated through its Power Supply Rejection (PSR) and transient response performance. The transient response performance mostly depends on the added buffer and the PSR performance depends on the pass device capacitance and the LDO loop gain.

PL

W artykule przedstawiono przegląd rozwiązań układów LDO (Low Drop Pout) w technologii CMOS. Przedstawiono także rozwiązania typu PSR – Power Supply Rejection. Analizowano dynamikę tych układów.

13

Evolution of IC Switching Voltage Regulator

Rahman L. F., Rong L. M., Reaz M. B. I., Husain H., Marufuzzaman M.

Przegląd Elektrotechniczny

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2015

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R. 91, nr 10

154-160

EN

To satisfy the fast voltage regulation and low input harmonic current distortion, a voltage regulator and a power factor correction (PFC) pre-regulator need to be existed. Cascading the voltage regulator with the PFC pre-regulator is the simplest way to implement the switching voltage regulator. The voltage regulator and PFC pre-regulator is processed the input power for switching regulator serially. The switching regulators efficiency has confirmed deteriorate. The requirement of the harmonic emission has been satisfied by the various types of the non-cascading PFC switching regulators. In this paper, the evolution of the switching regulator and various types of the non-cascading PFC switching regulator is discussed and the design of implementation of different output power levels for two types of non-cascading PFC switching regulator is presented.

PL

Do regulacji napięcia skuteczną metodą jest kaskadowe połączenie regulatorów napięcia I układów korekcji współczynnika mocy PFC. W artykule omówiono ewolucje różnych przełączalnych regulatorów napięcia. Przedstawiono też projekt i zastosowanie dwóch rodzajów regulatorów nie połączonych kaskadowo.

14

Power-saving voltage-to-current conversion with the use of CMOS differential amplifier

Wojtyna R.

International Journal of Microelectronics and Computer Science

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2015

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Vol. 6, nr 3

96--101

EN

Differential amplifiers are well known as input stage preamplifiers. This is because they exhibit the ability to reduce unwanted common-mode effects considerably. As a consequence, both noise and input signal of the amplifier can have low values. Proper operation of differential amplifiers is possible when implemented in chip form. For typical use of such CMOS amplifiers, input signals are delivered to differential-pair gate-terminals while tail terminal is used to ensure the required bias of the pair. The paper shows that the roles of gates and tail terminal can be changed. In other words, the tail current can be used as input signal while the gate ones as voltages controlling the amplifier gain. This enables to combine the achievable low noise with power efficient operation of the circuit. Necessary conditions for that are discussed in this paper. Suitability of atypically used differential amplifiers for voltage-to-current conversion is explained. Two examples of CMOS circuits implementing power economic conversion of this type are presented.

15

Low Voltage and Wide Bandwidth Class AB Variable Gain Amplifier in 0.18-μm CMOS Technology

Bhuiyan M. A. S., Idris M. I. B., Reaz M. B. I., Minhad K. N., Husain H.

Przegląd Elektrotechniczny

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2014

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R. 90, nr 6

184--187

EN

Variable gain amplifier (VGA) is the key element for amplifying process in analog to digital converter (ADC). In this paper, a low voltage and wide bandwidth class AB VGA is designed using CEDEC 0.18-μm CMOS process for high speed applications. The result show that, the designed VGA has a wide bandwidth of 100-MHz and consumes power less than 125uW at 1V supply voltage. From the results it is also evident that the circuit is capable of working with high linearity and wide bandwidth. The frequency response (Gain) and the wide bandwidth of this class AB VGA is better than previously reported class AB VGA. Smaller transistors are used to make the chip small and it occupies only 0.003 μm2. Such a VGA is suitable for high-performance RF devices.

PL

W artykule opisano niskonapięciowy, szerokopasmowy wzmacniacz klasy AB typu VGA (variable gain amplifier – wzmacniacz o zmiennym wzmocnieniu). Wzmacniacz zaprojektowano wykorzystując proces 0.18 um CMOS. Wykonano wzmacniacz o pasmie 100 mHz i poborze mocy mniejszym niż 125 uW przy napięciu zasilania 1 V.

16

Design and analyses of a low power linear voltage regulator in 0.18μm CMOS process

Amin S., Rong L. M., Reaz M. B. I., Hashim F. H., Kamal N.

Przegląd Elektrotechniczny

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2014

|

R. 90, nr 5

201--203

EN

Linear voltage regulator is inevitable in most electronic systems and demands low power and low area. A low dropout (LDO) linear voltage regulator is proposed in this paper by utilizing Current Feedback Amplifier (CFA) technology. The design achieves low power and low area by reducing the internal compensation capacitor and resistors. The simulated result shows that the design consumes only 567.1370pW which is 35% less than the reference circuit. The design also achieves low area and higher gain.

PL

W artykule omówiono liniowy regulator napięcia wykorzystujący koncepcję LDO (low dropout ). Układ wykorzystuje wzmacniacz z prądowym sprzężeniem zwrotnym CFA I technologię CMOS. Zrealizowano układ pobierający o 35% mniej energii niż układy znane z literatury.

17

An Integrated Analog Demultiplexer for Spatial Multiplexing of Local Elements Scheme Using MOS Transistors

Capovilla C. E., Araujo H. X., Kretly L. C.

Przegląd Elektrotechniczny

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2014

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R. 90, nr 3

115--118

EN

This paper proposes a CMOS analog demultiplexer for Spatial Multiplexing of Local Elements scheme at baseband level. This technique is a front-end receiver architecture which uses only one RF channel, carrying multiplexed information from multiple antennas into one RF single channel. The described circuit has four channels, in which each channel has a differential switch pair and an OTA for amplification and differential to single-ended signal conversion. The specifications and simulation performance are in close agreement, which validate the proposed compact design.

PL

W artykule zaprezentowano analogowy demultiplekser CMOS do przestrzennego multipleksowania (Spatial multiplexing). Ta technika jest stosowana w odbiornikach używających tylko jeden kanał RF i umożliwia multipleksowanie informacji z wielu anten. Opisany układ ma cztery kanały i każdy z kanałów ma różną parę kluczy.

18

A New Bandgap Voltage Reference Circuit using CMOS Differential Voltage Current Conveyor

Hongprasit S.

Przegląd Elektrotechniczny

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2014

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R. 90, nr 8

80-83

EN

This paper proposes a new approach of bandgap voltage reference (BGR) circuit design by using CMOS differential voltage current conveyor (DVCC). The proposed circuit employs single DVCC, which is able to reduce the number of devices used to bandgap core and start-up circuits. The simulation results indicate reference voltage of about 500mV, temperature coefficient (TC) of 20ppm/°C, which can be successfully operated with a minimum supply voltage of 1.2V in a temperature range of 0-100°C and a total power dissipation of 56.6 W at room temperature.

PL

Opisano pasmowy wzorzec napięcia NBGR zaprojektowany w technologii CMOS z wykorzystaniem układu DVCC (differentia voltage current conveyor).Zaprojektowany wzorzec umożliwia uzyskanie napięcia ok. 500 mV ze współczynnikiem temperaturowym 20 ppm/oC przy minimalnym napięciu zasilającym 1.2 V przy poborze mocy 56 uV.

19

Temperature-controlled oscillator and dedicated microcontroller for dynamic thermal management

Frankiewicz M., Kocanda P., Gal R, Kos A.

International Journal of Microelectronics and Computer Science

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2014

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Vol. 5, nr 2

81--86

EN

The paper describes UMC CMOS 0.18 pm (1.8 V) implementation of OctaLynx D microcontroller. The processor is 8-bit RISC structure with built-in Dynamic Thermal Management Unit cooperating with Temperature-Controlled Oscillator. The Dynamic Thermal Management Unit consists of clock source multiplexer, thermal interrupts control unit and special registers containing information of present chip temperature, oscillator frequency control signal and status/control bits. Processor core was written in Verilog hardware description language and designed in top-down technique while memories and analogue parts were designed in full custom technique. The system was fabricated and tested in the laboratory equipped with the thermal chamber. Some test results and software prepared for the microcontroller are presented.

20

Design of an Ultra-Low Power CT Σ∆ A/D Modulator in 65nm CMOS for Cardiac Pacemakers: From System Synthesis to Circuit Implementation

Wang Y., Cai H.

International Journal of Electronics and Telecommunications

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2014

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Vol. 60, No. 1

109-115

EN

A high performance, ultra-low power, fully differentia 2nd-order continuous-time Σ∆ analogue-to-digital modulator for cardiac pacemakers is presented in this paper. The entire design procedure is described in detail from the high-level system synthesis in both discrete and continuous-time domain, to the low-level circuit implementation of key functional blocks of the modulator. The power consumption of the designed modulator is rated at 182nA from a 1.2V power supply, meeting the ultra-low power requirement of the cardiac pacemaker applications. A 65nm CMOS technology is employed to implement the Σ∆ modulator. The modulator achieves a simulated SNR of 53.8dB over a 400 Hz signal bandwidth, with 32KHz sampling frequency and an oversampling ratio of 40. The active area of the modulator is 0.45×0.50mm².