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1
Content available Heat transfer simulations in the frequency domain with the application of thermal influence coefficients method
Gnidzińska K., Jabłoński G., Napieralski A., De Mey G
International Journal of Microelectronics and Computer Science
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2013
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Vol. 4, nr 4
164--169
EN
In this paper an extension of thermal influence coefficients method to frequency domain has been presented. The method allowed the steady-state analysis of three-dimensional heat flow in multilayered structures. The presented modelling is based on Fourier and Hankel transforms, two-port network theory and correction coefficients for close-area distances, allowing emulation of finite heat sources by infinitesimal ones.
2
Content available The aberrations of the AC thermal characteristics in the presence of solder defects in mltilayer microelectronic structures
Gnidzińska K.
International Journal of Microelectronics and Computer Science
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2011
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Vol. 2, nr 4
156-159
EN
In this paper, the multilayer microelectronic structures have been modeled using AC thermal modeling approach. The influence of defects in solder layers on the thermal parameters of the structures has been investigated. It has been presented how an aberration in a solder layer that may result e.g. from the manufacturing flaw, can significantly affect the thermal characteristics of the structure thus aggravating the conditions of the heat transfer. The phenomena have been described in the qualitative and quantitative way. Furthermore, the applicability of the proposed modeling method for the purpose of determining the optimal frequency range in non-destructive device testing technique - lock-in thermography - has been demonstrated.
3
Content available Heat dissipation and temperature distribution in long interconnect lines
Gnidzińska K., Mey G., Napieralski A.
Bulletin of the Polish Academy of Sciences. Technical Sciences
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2010
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Vol. 58, nr 1
119-124
EN
Thermal and time delay aspects of long interconnect lines have been investigated. To design a modern integrated circuit we need to focus on very long global interconnects in order to achieve the desired frequency and signal synchronization. The long interconnection lines introduce significant time delays and heat generation in the driver transistors. Introducing buffers helps to spread the heat production more homogenously along the line but consumes extra power and chip area. To ensure the functionality of the circuit, it is compulsory to give priority to the time delay aspect and then the optimized solution is found by making the power dissipation as homogenous as possible and consequently the temperature distribution T (relative to ambient) as low as possible. The technology used for simulations is 65 nm node. The occurring phenomena have been described in a quantitative and qualitative way.
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