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Current mode sigma-delta modulator designed with the help of transistor’s size optimization tool

Śniatała P., Naumowicz M., Handkiewicz A., Szczęsny S., Melo J. L. A., Paulino N., Goes J.

Bulletin of the Polish Academy of Sciences. Technical Sciences

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2015

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Vol. 63, nr 4

919--922

EN

The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 μW, which corresponds to an efficiency of 59.7 fJ/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.

2

Polyphase Comb Filter Based on Dispatching Input Bit-stream and Interlaying Multiplexer Techniques for Sigma-Delta ADCs

Abdollahvand S., Goes J., Paulino N., Gomes L.

International Journal of Microelectronics and Computer Science

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2012

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Vol. 3, nr 4

152-158

EN

This paper describes a new design approach for implementing a Polyphase Comb Filter (PCF) based on dispatching input bit-stream and interlaying multiplexer techniques. In order to make our solution more energy efficient in comparison with prior art, we start with a detailed analysis of the drawbacks and advantages of the existing classical techniques. A new structure based on a novel SINC3 design is proposed. This new design uses a controller unit to activate one sub-filter in each specific time interval. As a consequence, no input registers and switches are required. Since this decimation filter is working with a single-bit output bit-stream, the required multiplication function can be simply done by using interlaying multiplexers (MUXs). By interlaying different levels of MUXs along with the navigation of the input bit stream we can easily emulate the multiplication operation. The implementation in a Xilinx Spartan3 FPGA demonstrates the feasibility and hardware efficiency of our solution . The proposed new filter architecture can be readily applicable to any Sigma-Delta (ΣΔ) ADC with a single-bit output stream and it requires a reduced number of adders and registers when compared with the state-of-the-art approaches.

3

Analysis and Design of a First - Order Delta-Sigma Modulator based on Ultra Incomplete Settling and Considering Non-ideal Effects

Nowacki B., Paulino N., Goes J.

International Journal of Microelectronics and Computer Science

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2012

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Vol. 3, nr 4

125-131

EN

One of the main building blocks of a Delta-Sigma modulator (ΔΣ?) is the integrator circuit. Usually this is implemented either in discrete or in continuous time domains using amplifiers. This paper analyses a ΔΣcircuit based on the implementation of passive switched-capacitor (SC) integrator using ultra incomplete settling. The behavior of a 1st order ΔΣ? is fully analyzed and explained, as well as its non-ideal effects, which become more significant for higher clock frequencies. This work compares performance of ΔΣM clocked with Fclk=100 MHz and Fclk=300 MHz. Electrical simulations show that the ΔΣM (Fclk=300 MHz) achieves a peak signal-to-noise-plus-distortion ratio (SNDR) of 67.5 dB, a peak signal-to-noise ratio (SNR) of 69.7 dB for a signal with a bandwidth (BW) of 400 kHz, while dissipating only 232μW from a 1.1 V power supply voltage, resulting in a figure-of-merit (FOM) of 165 fJ/conv.-step (simulated).

4

Digitally programmable delay-locked-loop with variable charge pump current

Lopes B., Paulino N., Goes J., Steiger-Garçăo A.

International Journal of Microelectronics and Computer Science

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2010

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Vol. 1, nr 3

269-276

EN

This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. The architecture of the programmable delay uses a ΣΔ modulator to generate a reference clock with a delay unaffected by component matching. This reference clock has a large jitter noise component that is filtered by delay lock loop (DLL). The programmable delay can produce a delay ranging from 20 ns to 100 ns, because of the large delay variation, it is necessary to use a variable charge pump current in the DDL, in order to guaranty stability for all the desired delay values. The electrical design of the circuit, in a 0.13-/žm 1.2-V CMOS technology, will be presented, as well as electrical simulations results of the complete system.

5

Design of a 3rd order 1.5-bit continuous-time (CT) sigma-delta (ΣΔ) modulator optimized for class D audio power amplifier

de Melo J., Paulino N.

International Journal of Microelectronics and Computer Science

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2010

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Vol. 1, nr 2

156-164

EN

This paper presents a 3rd order 1.5-bit ΣΔ modulator with distributed feedback and local resonator feedback for a Class D audio amplifier. In order to improve the signal-to-noise-and-distortion ratio (SNDR), without increasing the oversampling ratio (OSR) or the order of the modulator, the modulator uses transmission zeros and 1.5-bit quantization. High level simulations of the modulator architecture show that it has a maximum SNDR value of 81 dB, for a signal bandwidth of 18 kHz and a sampling frequency of 1.2 MHz. An electrical circuit is designed to implement the proposed architecture and the electrical simulations show that it has a maximum SNDR value of 76.1 dB. The influence of the constituting blocks of the circuit in the performance of the modulator is investigated using electrical simulations.

6

A MOSFET only, step-up DC DC micro power converter, for solar energy harvesting applications

Carvalho C., Paulino N.

International Journal of Microelectronics and Computer Science

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2010

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Vol. 1, nr 2

112-119

EN

In this paper, a step-up micro power converter for solar energy harvesting applications is presented. The circuit is based on a switched-capacitor voltage doubler architecture with MOSFET capacitors, which results in an area approximately eight times smaller than using MiM capacitors for the 0.13 žm CMOS technology. In order to compensate for the loss of efficiency, due to the larger parasitic capacitances, a charge reutilization scheme is employed. The circuit uses a phase controller, designed specifically to work with the series of two PV cells, in order to regulate the output voltage to 1.2 V. Electrical simulations of the circuit, together with an equivalent electrical model of a PV cell, show that the circuit can deliver a power of 536.1 žW to the load, while drawing a power of 799.8 žW from two PV cells stacked in series, corresponding to a maximum efficiency of 67%.