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Caliburn: a MIPS32 VLIW Processor with Hardware Instruction Morphing Mechanism

Chu S.-L., Li G.-S., Liu R.-Q.

Przegląd Elektrotechniczny

2013

R. 89, nr 3b

10--12

This work proposes a novel quad-issue VLIW architecture, called Caliburn, for directly executing legacy MIPS32 binary programs. To schedule and pack legacy MIPS32 binary codes on-the-fly, Caliburn has an integrated novel hardware instruction morphing mechanism that converts legacy MIPS32 binary instructions into a VLIW instruction bundles without the intervention of software compilers. The performance enhancement of Caliburn with a pipelined MIPS32 processor is evaluated. The Caliburn VLIW processor is implemented using Bluespec SystemVerilog HDL and synthesized using Synopsys Design Compiler. The experimental result reveals that the Caliburn processor achieves 3.08X speedup, and can be operated at a frequency of 425 MHz by the fabrication of TSMC 40nm technology library.

W artykule przedstawiono propozycję nowej struktury VLIW na potrzeby wykonywania programów w architekturze MIPS32. W rozwiązaniu zastosowano technikę morfingu, w celu eliminacji programowych kompilatorów. Wykonano badania eksperymentalne na procesorze MIPS32, potwierdzające efektywność i szybkość opracowanej architektury.

Design a High-Performance Memory Controller for a Multimedia SOC

Chu S.-L., Lo M.-J.

Przegląd Elektrotechniczny

2012

R. 88, nr 7b

353--356

Continuously growing functionalities of modern consuming electronics make the major multimedia SOC (system-on-a-chip) chip more complex. Moreover, the integrated multimedia processors and the required memory bandwidth are increasing. Therein how to improve the performance of the memory controller will become a major challenge of designing a modern multimedia SOC. According to our previous study of multimedia SOC, to achieving the bandwidth requirements are not only by improving memory throughput but also by dynamically adjusting the bandwidth usage of multimedia processors. Therefore we develop novel memory subsystem, called Smart Memory Controller (SMC), which integrates a novel scheduling/arbitration mechanism, a unified access buffer, multi-level memory access classification/scheduling, and several corresponding hardware modules, to provide a sufficient memory bandwidth for the multimedia processors with high bandwidth requirements. The proposed SMC architecture has been implemented by SystemC/Bluespec/Verilog HDL. The experimental results from whole SMC system illustrates that SMC will arrange enough bandwidth for the channels that have bursting transferring requirement. The fabrication results of SMC are also provided.

W artykule zaproponowano nowy system pamięci nazwany SMC (smart memory controller) przeznaczony do multimedialnych elementów typu SOC (system on a chip). System integruje mechanizm planowania i arbitrażu (scheduling/arbitration), bufor dostępu, wielopoziomowy dostęp do pamięci i wiele innych modułów.