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2 Electronics and Telecommunications Quarterly

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Co-Design Strategy Approach of LNA, Oscillator, and Mixer

Oliveira J. P., Oliveira L., Ferreira J. J., Bastos I., Michalak T., Pankiewicz P., Nowacki B., Makosa P., Rybarczyk A.

Electronics and Telecommunications Quarterly

2009

Vol. 55, No 4

585-599

A co-design strategy for the implementation of a low-voltage fully integrated CMOS receiver is presented. This co-design approach allows the design of a compact direct-conversion receiver by avoiding 50 α matching buffers and networks, and AC coupling capacitors between mixer inputs and LNA and oscillator outputs. Moreover, the proposed circuit does not require DC choke inductors for mixer biasing. Since a 1.2 V power supply is used, a current bleeding technique is applied in the LNA and in the mixer. To avoid inductors and obtain differential quadrature outputs, an RC two-integrator oscillator is employed, in which, a filtering technique is applied to reduce phase noise and distortion. The proposed receiver is designed and simulated in a 130 nm standard CMOS technology. The overall conversion voltage gain has a maximum of 35.8 dB and a noise figure below 6.2 dB.

Hardware architecture of a parallel system for lane detection

Pankiewicz P., Powiertowski W., Roszak G.

Electronics and Telecommunications Quarterly

2008

Vol. 54, No 4

547-560

The aim of this paper is to describe in detail the hardware implementation of the lane detection algorithm presented at 15th International Conference "Mixed Design of Integrated Circuits and Systems". During introductory research several approaches to edge and line detection were analyzed, which resulted in optimal combination for future hardware implementation. The proposed algorithm is based on the Canny edge detector and the linear Hough transform for line detection. The system was pre-developed using the Matlab environment. The next step was the synthesizable hardware description using VHDL. A wide range of testing procedures for structural and behavioral verification was designed. The presented evaluation of both hardware and software simulation, and synthesis results suggested high capabilities of designed architecture, which have been proven during real-time hardware tests of the system.