Wyniki wyszukiwania - BazTech

1

Hierarchical Fast Selection of Intraframe Prediction Mode in HEVC

Siast J., Stankowski J., Domański M.

International Journal of Electronics and Telecommunications

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2016

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Vol. 62, No. 2

147--151

EN

In the new HEVC standard, there are 35 intraframe prediction modes. Therefore, real-time implementations need fast mode pre-selection to reduce the computational load of cost comparison for individual modes. In this paper, a simple technique is proposed to reduce the complexity of the Unified Intra Prediction by decreasing the mode candidate number evaluated in the Rough Mode Decision step. We call this approach hierarchical as we decrease stepwise the angles between the directions of the prediction modes that are tested. Obviously, the fast mode selection results in significant complexity reduction obtained at the cost of choosing a sub-optimum mode related to slightly reduced compression performance. In the paper, it is proposed how to calculate the trade-off between encoder complexity and compression performance, using the ratio of relative coding time reduction and average bitrate increase estimated for constant decoded video quality. Extensive experiments prove that this ratio is much higher for the proposed technique than for many other techniques from the references.

2

Analysis of Compressed Data Stream Content in HEVC Video Encoder

Stankowski J., Karwowski D., Grajek T., Wegner K., Siast J., Klimaszewski K., Stankiewicz O., Domański M.

International Journal of Electronics and Telecommunications

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2015

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Vol. 61, No. 2

121-127

EN

In this paper, a detailed analysis of the content of the bitstream, produced by the HEVC video encoder is presented. With the use of the HM 10.0 reference software the following statistics were investigated: 1) the amount of data in the encoded stream related to individual frame types, 2) the relationship between the value of the QP and the size of the bitstream at the output of the encoder, 3) contribution of individual types of data to I and B frames. The above mentioned aspects have been thoroughly explored for a wide range of target bitrates. The obtained results became the basis for highlighting guidelines that allow for efficient bitrate control in the HEVC encoder.

3

Poznański kodek obrazów trójwymiarowych

Grajek T., Karwowski D., Klimaszewski K., Konieczny J., Kurc M., Łuczak A., Ratajczak R., Siast J., Stankiewicz O., Stankowski J., Wegner K.

Przegląd Telekomunikacyjny + Wiadomości Telekomunikacyjne

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2013

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nr 2-3

81--83

PL

W tym artykule prezentujemy oryginalną technologię kompresji, która została zaprojektowana i opracowana na Politechnice Poznańskiej w odpowiedzi na zaproszenia do składania wniosków MPEG Technologia Kodowania Wideo 3D. W niezależnych testach wniosek został oceniony jako jeden z najlepszych. Baza jest kodowana w HEVC podczas gdy mapy są zakodowane wykorzystując różne zwolnienia, które są podobne do poszczególnych widoków i map głębi. Nawet 2 widoki z boku i 3 głębokości mapy mogą być kodowane w całkowitej wartości bitowej, co zazwyczaj nie przekracza 50% prędkości transmisji danych potrzebnych do jednego widoku.

EN

In this paper, we present the original compression technology that was designed and developed at Poznań University of Technology in response to MPEG Call for Proposals on 3D Video Coding Technology. In the independent tests, this proposal was scored as one of the best performing ones. A base view is coded in the HEVC syntax while the side views and the depth maps are very efficiently coded exploiting various redundancies that are related to similarities between individual views and depth maps. Even 2 side views and 3 depth maps can be coded at the total bitrate that usually does not exceed 50% of the bitrate needed for a single view.

4

Network-on-Multi-Chip (NoMC) with Monitoring and Debugging Support

Łuczak A., Stępniewski M., Siast J., Domański M., Stankiewicz O., Kurc M., Konieczny J.

Journal of Telecommunications and Information Technology

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2011

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nr 3

81-86

EN

This paper summarizes recent research on network-on-multi-chip (NoMC) at Poznań University of Technology. The proposed network architecture supports hierarchical addressing and multicast transition mode. Such an approach provides new debugging functionality hardly attainable in classical hardware testing methodology. A multicast transmission also enables real-time packet monitoring. The introduced features of NoC network allow to elaborate a model of hardware video codec that utilizes distributed processing on many FPGAs. Final performance of the designed network was assessed using a model of AVC coder and multi-FPGA platforms. In such a system, the introduced multicast transmission mode yields overall gain of bandwidth up to 30%. Moreover, synthesis results show that the basic network components designed in Verilog language are suitable and easily synthesizable for FPGA devices.

5

Szeregowy interfejs komunikacyjny dla układów FPGA serii Virtex

Łuczak A., Kurc M., Siast J.

Pomiary Automatyka Kontrola

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2010

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R. 56, nr 7

749-751

PL

Artykuł przedstawia implementację sprzętową szeregowego interfejsu komunikacyjnego dla układów FPGA firmy Xilinx z serii Virtex. Rozwiązanie opiera się na wbudowanych w układy tej serii moduły SERDES i jest dedykowane dla zastosowań wymagających dużych przepływności. Interfejs charakteryzuje się skalowalnością, oraz możliwością pracy w osobnej domenie częstotliwościowej. Proponowane moduły zostały przetestowane w symulacjach, oraz w układzie sprzętowym.

EN

The paper presents hardware implementation of serial communication interface for Xilinx Virtex series programmable devices. The proposed solution is based on embedded SERDES modules of these devices and shows practical realisation of fast interface for multimedia purposes, where high bitrates are required. The interface is scalable and has ability to operate in a separate clock frequency domain, which allows flexible modification of its parameters according to the project requirements. The receiver and transmitter architecture is presented in paragraph 2. There is also described the way of dividing the transmitted data into transition flits, the method for ensuring synchronization and theoretical throughput of the developed link. The proposed modules were tested by simulations and hardware implementation (see paragraph 3). Tables 1 and 2 contain the synthesis results for different FPGAs. A new application model consisting of a video camera as a source of the transmitted signal and starter boards with Virtex FPGAs as processing devices is presented. The worked out interface is used for connecting boards. Its proper work is proved by visual observation of the transmitted and processed video data presented on LCD displays mounted on two system starter boards. The false rate level for the transmitted data was also computed. It is given in Table 3.