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1

Evolution of Low Drop Out Voltage Regulator in CMOS Technologies

Mustafa N. B., Amin S., Reaz M. B. I., Hashim F. H., Kamal N.

Przegląd Elektrotechniczny

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2015

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R. 91, nr 12

26-33

EN

The demand for low voltage devices has initiated the development of Low Drop Out (LDO) regulator in manifold. This paper presents a review of various LDO frameworks that have been implemented in CMOS technologies and the impact of frameworks related to the parameters of the LDO. The LDO architecture is evaluated through its Power Supply Rejection (PSR) and transient response performance. The transient response performance mostly depends on the added buffer and the PSR performance depends on the pass device capacitance and the LDO loop gain.

PL

W artykule przedstawiono przegląd rozwiązań układów LDO (Low Drop Pout) w technologii CMOS. Przedstawiono także rozwiązania typu PSR – Power Supply Rejection. Analizowano dynamikę tych układów.

2

Design and analyses of a low power linear voltage regulator in 0.18μm CMOS process

Amin S., Rong L. M., Reaz M. B. I., Hashim F. H., Kamal N.

Przegląd Elektrotechniczny

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2014

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R. 90, nr 5

201--203

EN

Linear voltage regulator is inevitable in most electronic systems and demands low power and low area. A low dropout (LDO) linear voltage regulator is proposed in this paper by utilizing Current Feedback Amplifier (CFA) technology. The design achieves low power and low area by reducing the internal compensation capacitor and resistors. The simulated result shows that the design consumes only 567.1370pW which is 35% less than the reference circuit. The design also achieves low area and higher gain.

PL

W artykule omówiono liniowy regulator napięcia wykorzystujący koncepcję LDO (low dropout ). Układ wykorzystuje wzmacniacz z prądowym sprzężeniem zwrotnym CFA I technologię CMOS. Zrealizowano układ pobierający o 35% mniej energii niż układy znane z literatury.

3

A transputer implementation of systolic arrays design for low-level medical image processing

Amin S., Saeed M.

Image Processing & Communications

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2000

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Vol. 6, no 3-4

35-45

EN

Many low-level image processing operations, termed local operators, require access to the four or eight neighbouring intensity values of a pixel, when computing the new value for the pixel and need large amounts of computing i.e., banded matrix operations. However, these algorithms contain explicit parallelism which can be efficiently exploited by processor arrays. The purpose of this paper is to identify a set of systolic array designs suitable for implementing low level image processing algorithms for medical images of tissues on VLSI processing arrays, in particular we consider the sigma, inverse gradient and mean filters. To achieve high performance we have developed several models of systolic arrays. One of the aims of this is to design and build a programming workbench for developing image processing operations for low-level vision. The motivation for the work is to develop a methodology for the implementation of an image processing library on the Transputer network, which holds a library of precoded software components in a generalised configuration-independent style for medical images. The digital image processing filter library is discussed in thispaper.